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SJIT, Solder Joint Integrity Test, To Find Latent Defects in Printed Wiring Board Assembly
April 29, 2015 | Hiroshi Yamazaki, Hioki E.E. CorporationEstimated reading time: 5 minutes
Latent defect test
The defects that come out after a PWBA is delivered to customers are called "Latent defect". In automotive industries for example, latent defect may happen if any solder joint is not complete. While driving a car, the PWBA inside suffers vibration and the solder joint without solder or with insufficient solder may become complete open.Thus even though there is not a failure in an initial stage, defect happens sometimes after long time due to a latent effect.
Basics of SJIT, Solder Joint Integrity Test
The purpose of SKIT is to find latent defects. There are some ways to find IC pin opens, but conventional capacitive, magnetic and diode methods cannot find latent pin opens. Also, boundary-scan test can find IC pin opens, but cannot find latent pin opens. X-ray test can find latent pin opens, but it is too slow to test a whole board assembly.
The only practical way to fine latent defects is 4-wire resistance measurement method.. The less the volume of solder is, the more resistance becomes. By measuring resistance across solder joint, therefore reliability of solder joint can be tested.
Case studies of SJIT
In the following pages, some solder conditions and measured resistance are shown.
Conclusion
Repair cost enormously increases if a defect is found in downstream. It is called "The 10X rule in PWBA tests". This rule means that PWBAs need to screen out defectives in an early stage by structural tests.
Even if a defect is found in the market, recall cost can be 1million times or more, so in the structural test at the assembly factory, need to screen out latent defectives as well.
SJIT, Solder Joint Integrity Test, is to find latent defects, and 4-wire resistance measurement method is the only way to find them at the moment
References
[1] Hiroshi YAMAZAKI, "Key Drivers and Challenges for Electronics Packaging Test and Inspections", The Japan Institute of Electronics Packaging, Vol. 14, No. 1, 2011, pp. 26-30
[2] Koji UCHIYAMA, "Preparation for Test/Inspection Economical Scale", The Japan Institute of Electronics Packaging, Vol. 14, No. 2, 2011, pp. 103-108
Editor's Note: This article was originally presented at the 2014 IPC APEX EXPO Technical Conference Proceedings.
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