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Perhaps one of the three most fundamental aspects of printed circuit fabrication is the metallization and electroplating of throughhole vias and blind via interconnections. Ideally, one should also include fine-line imaging of increasingly smaller feature sizes and via formation, whether by mechanical or laser methods.
Indeed, the foundation of technology roadmaps should, at the very least, encompass a discussion of line widths and spaces, PTH and blind via aspect ratios, and a metric that defines acceptability of plating uniformity and throwing power. These same parameters have been used for nearly four decades to quickly quantify the capability of a fabricator to profitably produce traditional boards. The ability to image conductor lines, and perhaps even more important, the insulating airspace between them, is considered a key characteristic. With surface mount components, a dramatic decrease in plated via hole diameter requirements occurred, and as a result, via holes have become simple vertical interconnections. Now, under competition from laser drilling, both drill bit and machine technology have driven mechanical holes capability much smaller.
In the most recent release of the IPC Technology Roadmap, PTH and blind via diameters and aspect ratios have been defined as to the technology sector where the boards are used. In order to provide a list of key attributes (layer counts, board thickness, number and diameters of vias, etc.) for the PCB, emulators are employed. Emulators (synthetic) are representations of a category of product, combining the attributes common to the type to avoid concerns about disclosure of specific company-proprietary designs. Technologists from around the world were asked to provide their respective view of the PCB technology required for the emulator. This exercise is critical in developing and understanding roadmaps.
Editor's Note: This article originally appeared in the May 2015 issue of The PCB Magazine.
