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Stanford-led Skyscraper-style Chip Design Boosts Electronic Performance by Factor of a Thousand
December 11, 2015 | Stanford UniversityEstimated reading time: 4 minutes
Mitra and Wong have already demonstrated a working prototype of a high-rise chip. At the International Electron Devices Meeting in December 2014 they unveiled a four-layered chip made up of two layers of RRAM memory sandwiched between two layers of CNTs.
In their N3XT paper they ran simulations showing how their high-rise approach was a thousand times more efficient in carrying out many important and highly demanding industrial software applications.
Stanford computer scientist and N3XT co-author Chris Ré, who recently won a "genius grant" from the John D. and Catherine T. MacArthur Foundation, said he joined the N3XT collaboration to make sure that computing doesn’t enter what some call a "dark data" era.
"There are huge volumes of data that sit within our reach and are relevant to some of society's most pressing problems from health care to climate change, but we lack the computational horsepower to bring this data to light and use it," Re said. “As we all hope in the N3XT project, we may have to boost horsepower to solve some of these pressing challenges.”
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