Elementary, Mr. Watson: Rules of Thumb—Guidelines vs. Principles for PCB Design
Global PCB Connections: A Technical Overview of Long-flex Printed Circuit Boards
Beyond Design: DDR3/4 Fly-by vs. T-topology Routing
June 1, 2016 | Barry Olney, In-Circuit Design Pty LtdEstimated reading time: 1 minute
JEDEC introduced fly-by topology in the DDR3 specification for the differential clock, address, command and control signals. The advantage of fly-by topology is that it supports higher-frequency operation, reduces the quantity and length of stubs and consequently improves signal integrity and timing on heavily loaded signals. Fly-by topology also reduces simultaneous switching noise (SSN) by deliberately causing flight-time skew, between the address group and the point-to-point topology signals, of the data groups. To account for this skew, the DDR3/4 controller supports write leveling. The controller must add the write leveling delays to each byte lane to maintain the strobe to clock requirement at the SDRAMs.
T-topology can be challenging to route, particularly double T-topology with four back-to-back SDRAMs, but it can be advantageous when using multi-die packages. The fly-by topology used in Figure 3 is much easier to route but does not work well with high-capacitance loads, such as LPDDR3 DDP (double die package) and QDP (quad die package) devices. IC fabricators basically arrange dies in parallel to increase package density which can also increase input capacitance by up to four times. Excessive ring-back is often present in the first few nodes of the daisy chain.
This is the reason why the T-topology was developed. However, if you are supporting only SDP (single die package) devices, then the fly-by is the most straightforward approach. It doesn't matter which topology you use, though—both fly-by and double T-topologies should work fine. If you are using a DDP device, then double-T topology works better than fly-by in terms of delivering a better system margin.
During a write cycle, using the fly-by topology, data strobe groups are launched at separate intervals to coincide with the clock arriving at memory components on the SODIMM or PCB, and must meet the timing parameter between the memory clock and DQS defined as tDQSS of ± 0.25 tCK. The PCB design process can be simplified using the leveling feature of the DDR3/4. The fly-by, daisy chain topology increases the complexity of the controller design to achieve leveling but fortunately, greatly improves performance and eases board layout for DDR3/4 designs.
To read this entire article, which appeared in the April 2016 issue of The PCB Design Magazine, click here.
Share on:
Suggested Items
PCB Layout Rules of Thumb for Consideration
11/25/2024 | Patrick Davis, Cadence Design SystemsJust because a “rule of thumb” is usually based on experience instead of precise facts doesn’t negate its value. For instance, when I told my kids that a good rule of thumb was not to back-talk to their mother, they discovered very quickly how accurate my advice was once they crossed that line. There are a lot of rules of thumb that we rely on daily, including those that apply to PCB design.
HPC Customer Engages Sondrel for High End Chip Design
11/25/2024 | SondrelSondrel, a leading provider of ultra-complex custom chips, has announced that it has started front end, RTL design and verification work on a high-performance computing (HPC) chip project for a major new customer.
Rules of Thumb for PCB Layout
11/21/2024 | Andy Shaughnessy, I-Connect007The dictionary defines a “rule of thumb” as “a broadly accurate guide or principle, based on experience or practice rather than theory.” Rules of thumb are often the foundation of a PCB designer’s thought process when tackling a layout. Ultimately, a product spec or design guideline will provide the detailed design guidance, but rules of thumb can help to provide the general guidance that will help to streamline the layout process and avoid design or manufacturing issues.
PCB Design Software Market Expected to Hit $9.2B by 2031
11/21/2024 | openPRThis report provides an overview of the PCB design software market, detailing key market drivers, challenges, technological advancements, regional dynamics, and future trends. With a projected compound annual growth rate (CAGR) of 13.4% from 2024 to 2031, the market is expected to grow from $3.9 billion in 2024 to $9.2 billion by 2031.
KYZEN to Spotlight KYZEN E5631, AQUANOX A4618 and Process Control at SMTA Silicon Valley Expo and Tech Forum
11/21/2024 | KYZEN'KYZEN, the global leader in innovative environmentally friendly cleaning chemistries, will exhibit at the SMTA Silicon Valley Expo & Tech Forum on Thursday, December 5, 2024 at the Fremont Marriott Silicon Valley in Fremont, CA.