Global Technology Development: HDP User Group European Meeting 2016

Estimated reading time: 16 minutes

After a break for lunch, the session on new infrastructure projects began with Marika Immonen from TTM giving a status update on the Optical Interconnect Phase 2 project, which was at the definition stage, but shortly to move to implementation. The first phase of the project had evaluated the feasibility of optical waveguide based technologies on PCBs, examined optical fibre and waveguide link characteristics and connectivity options, and determined performance benefits and limitations using polymer waveguides and fibres. The second phase was a 19” rack demonstrator, with backplane, daughter cards and mezzanine card variants with optical engines and high speed RF connectors, to enable optical and electrical testing using state-of-the-art technologies from multiple sources. Almost fifty companies had shown an interest in participating in the project, and collaboration with the EU-funded PhoxTroT project provided HDP User Group members with access to European optical technologies and the opportunity to share testing resources. Immonen explained that the industry had moved to multiple solutions, and a choice of optical technologies was available. She described free standing flexible, embedded glass and embedded polymer waveguide interconnects, all of which could be incorporated into the demonstrator. She then discussed design and specification details of backplane, daughter and mezzanine cards, which were separate for the two consortia, although the logic cards would be accessible to both. The testing plan included passive direct insertion loss testing, passive insertion loss testing, active direct testing, partial link testing and full link testing. Most of the parts and components had now been sourced, and assembly was in progress with a target date of mid-June 2016.

The second New Infrastructure topic to be discussed was Phase 3 of the Anti-Counterfeit of Electronics project, at the definition stage, and its status was reported in a call-in from HDP User Group facilitator Laurence Schultz. Previous phases had resulted in the development of a minimum data set for communication within the electronics supply chain, against which the open and commercially available anti-counterfeiting technologies had been evaluated and their optimal application areas identified. A detailed report was available to HDP User Group members. In Phase 3, the anti-counterfeiting team proposed to investigate the current traceability best practices of the electronics supply chain, and to compare them to the recommendations from phases 1 and 2. This required soliciting sensitive information from member companies, and it was recommended that HDP User Group engage an independent third party to conduct the survey and anonymise the respondents to protect intellectual property and trade secrets. Most companies were interested in the counterfeit topic, but the problem was too broad to motivate participation, so a pro-active approach was advocated. The team was currently creating the survey questionnaire.

Laurence Schulz stayed on the call-in line to update the meeting on the Digital Image Speckle Correlation (DISC) project, currently at the idea phase. There was considerable interest in predicting the reliability of stacked microvia designs under lead-free assembly conditions, particularly the effects of structural features such as the number of stacks, the pitch between the vias, and whether the microvias were stacked on or off a buried via. Typical failure mechanisms were microvia separation, interfacial delamination and copper fatigue failure. The DISC project was a physics-based study, based on a unique method of quantitative measurement of thermal stress in microvias and surrounding areas, and mechanistic failure analysis. The project would compare results with the accelerated thermal cycling data from the Multi-Lam project, with three specific design categories: high-CTE 18-layer 3-stack “off-buried,” low-CTE 12-layer via stack “on-buried” and high-CTE 18-layer via stack “on-buried.” Samples would be prepared for digital speckle correlation testing and then the test method would be applied to determine whether it could predict the reversal of some of the failure mechanisms.

Laminate expert Alun Morgan took the stage again, this time to report on the Design Related PWB Material Damage project, specifically to assess the impact of the lead-free soldering process on latest-generation PWB laminates, to determine their suitability for high layer count and high thermal mass board designs in which board the surface could see temperatures up to 260°C during reflow, and to understand the impact of layer count, resin content and through-via pitch on the risk of delamination. Testing was being conducted by PWB Interconnect Solutions using their Dielectric Estimation Laminate Assessment Method (DELAM). Morgan explained why 6 cycles at 260°C had been chosen as the test condition, on the basis that complex, high reliability infrastructure products were typically thick multi-layers with densely packed components including large ceramic devices, and in order to achieve a lead-free reflow temperature of 235°C on the high-thermal-mass components, some areas of the board saw temperatures up to 260°C. And such assemblies were typically double-sided SMT, often with additional selective soldering and rework requirements. Therefore six cycles represented a meaningful worst-case scenario. Good correlation had been observed between capacitance results and cross-section analysis, confirming that capacitance measurement was a valuable tool to detect internal damage and that visual inspection alone could not be relied upon. Morgan showed examples of adhesive and cohesive delamination detected by the DELAM method. Future project goals were to quantify the impact of board design on the resistance to delamination of PWBs through the lead-free SMT process: the effects of via pitch, board thickness, number of layers, resin content, presence of additional central plane layers, and to further evaluate specific materials to identify their limits. 19 companies were participating in the project.

Each of the project presentations generated plenty of interactive discussion, and in each case a sign-up sheet was passed around the group so that members could register their interest in joining a particular project consortium. Jack Fisher informed the meeting that HDP User Group currently had 27 active projects, of which one in idea stage, 10 in definition and 16 in implementation. In addition, there was a queue of potential projects that might move into the idea stage within the coming few months. He commented that member feedback had indicated that the process for new project ideas could be made more efficient. Some members felt that that they had insufficient information on which to make a decision, and some wanted more information to take back to their company to discuss with their colleagues. Therefore a modified approach had been taken, and at the meeting three new project suggestions were offered for consideration, in the form of short presentations by the proposers, with the slides included in the take-home pack. Jack Fisher proposed, on behalf of Bill Birch from PWB Interconnect Solutions, a project on embedded device reliability. Jack Tan, HDP User Group’s Asia representative, proposed a project on solder joint reliability with ENEPIG as the solderable finish, and Dave Love proposed taking a new direction in the through-silicon via project.

After the close of the afternoon session, the group travelled by coach to Wiltz, about one hour to the north, for a guided tour of the factory of Circuit Foil, and gained an understanding of the manufacturing process for electrodeposited copper foil, the fundamental basis of the printed circuit interconnect.

The day was long and technically intense. For me, it was a return visit to the open session of HDP User Group’s European meeting, so I had a fairly clear idea what to expect in terms of format and content and I certainly learned a lot. But it was the spirit of community and the willingness of people to share their knowledge, their skills and resources that once again impressed me most. Thank you HDP User Group for making me so welcome.

I am grateful to Alun Morgan for allowing me to use his photographs.

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