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Substrates for Advanced PCB Technologies: What Will the Future Hold?
November 6, 2018 | Pete Starkey, I-Connect007Estimated reading time: 9 minutes
The UK chapter of the global IMAPS community of electronics and microelectronic packaging engineers shared a wealth of knowledge and wisdom about PCB substrate technology trends, developments, and future requirements in a webinar on the first of November. The webinar was introduced on behalf of IMAPS-UK by National Physical Laboratory’s electronics interconnection expert Martin Wickham and featured presentations by Piers Tremlett and Jim Francey.
“Who knows which future substrate will be successful?” Aware of a need to exercise caution when attempting predictions, Piers Tremlett, engineering specialist at Microsemi, quoted an example from ancient Greece: “The Oracle at Delphi knew how to error-proof her future predictions. Everyone else gets it wrong; it’s just a question of by how much.” Nevertheless, his presentation painted a very clear picture of the future for printed circuit substrates, even exploring the possibilities for “substrateless” circuits.
Driven by a need to satisfy the desires of users, substrate technology aimed to improve performance and eliminate waste whilst minimising cost. Tremlett discussed the fluidity of future circuit structures, the potential growth of flexible substrates, the rise in substrates for handling power and heat, and trends from two-dimensional to three-dimensional circuit assemblies. He focused on four relevant topics: miniaturisation for mobile products, heat and power, printed electronics, and substrateless circuits.
Mobile products, especially smartphones, and the cost savings of using less material were the primary drivers for miniaturisation. As an example, Tremlett showed a cross-section of an iPhone 7 with a coreless 10-layer 500-micron substrate and sub-20-micron tracks densely populated with components and a lot of interconnect in a very small space. The interconnect was realised by semi-additive processing, pattern plating on a very thin base copper, and flash etching. As laser direct imaging capability improved and track widths trended towards 10 microns, it was preferred to embed them into the substrate surface to improve reliability, as demonstrated by the Daisho Denshi ultra-narrow pitch flush pad interposer. In his iPhone 7 example, the memory chip was mounted on a very thin three-layer PCB, underneath which was the processor chip with no substrate as such—all the tracks were laid on the packaging material itself and had produced significant performance improvements. He commented that fan-out wafer-level packaging was moving from silicon wafer technology to PCB technology with more than one component inside the mould compound, which could be seen as a paradigm shift away from FR-4 and surface mount.
Conventional assembly technology was giving way to embedded die technology and ultra-thin chip technology, leading to smaller and thinner devices. But whereas the trend had always been to push components off the PCB and on to the silicon, this was now becoming a more expensive option, and the components were being pushed back up into the packaging fab to continue the drive towards integration. Packaging was moving towards complete subsystems, placing more emphasis on substrate capability in terms of layer count and track width and presenting considerable competition to conventional PCB concepts.
Tremlett turned his attention to thermal management, increasing heat being generated by faster processors, RF chips, power chips and LEDs. It was becoming less practicable to use ceramic substrates except for special applications because of considerations of cost, small panel geometries, and high-temperature processing. So, could organic substrates be used as alternatives? He discussed thermal via designs, several forms of integrated metal substrates, metal inserts, and even water-cooled PCBs, and compared their efficiencies as a means of heat dissipation. He reviewed innovations in chip embedding for power packaging that had proven benefits for low- and high-power analogue and digital and RF products and described proprietary embedding package solutions such as SESUB and aEASI. The EmPower project was an international consortium developing embedded power semiconductors for the drive electronics in electric vehicle applications in a module that enabled heat removal on both sides over the shortest possible heat conduction paths.
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02/11/2026 | Brian Buyea -- Column: Powering the FutureCeramic packaging has quietly powered the electronics revolution for more than half a century. From the earliest thick-film hybrids to today’s direct bond copper (DBC) substrates and metallized aluminum nitride, every step forward in ceramic technology has pushed the limits of reliability, power density, and performance. It’s essential for every design engineer building the next generation of electronic systems to understand this evolution.
Fresh PCB Concepts: Cost Stability in a Period of Copper and Gold Volatility
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Connect the Dots: The Future of Designing for Reality—Pattern Plating
02/05/2026 | Matt Stevenson -- Column: Connect the DotsLast month, I discussed the outer-layer imaging process and offered tips for designers to help ensure smooth manufacturing and high-quality output. The next step in the manufacturing process is copper pattern plating, where fabrication can be tricky, and design precision is even more important. The board is now ready to have the copper traces, through-holes, vias, pads, and other elements specified in the original CAD design plated to copper thickness requirements. I will identify some key design considerations for pattern plating, break down the process, and offer design tips for a successful outcome.
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