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iNEMI Call for Participation Webinar Dec. 12December 6, 2019 | iNEMI
Estimated reading time: 1 minute
Flip chip electronic packages are commonly used to address today’s high-density interconnect needs. However, the formation of small voids (microvoids) can occur in solder-based flip chip joints during the assembly process and these voids tend to grow after multiple reflows. This can be a concern for certain applications that involve high electrical and thermal flux across the flip chip where void formation can have an impact on electromigration in the joint. The presence of a void can accelerate complete open failure due to electromigration.
This project will study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. The project will have two distinct phases:
- Phase 1: Determine recommended inspection capabilities for micro-voids in 1st level interconnect materials
- Phase 2: Determine the relationship between voids and the electrical and mechanical reliability of the assembly
The project is expected to develop technical guidelines regarding acceptable voiding characteristics for flip chip interconnects that can be shared with industry and relevant standards bodies.
The 1st Level Interconnect Void Characterization Project is led by Lee Kor Oon (Intel) as project leader, with Sze Pei Lim (Indium) and Kiyoshi Ooi (Shinko) as co-leaders. Click here for additional project information.
If you are interested in this project, please join us for one of our call-for-participation webinars. These webinars are open to industry (iNEMI membership is not required). Participants must register in advance. Click on the links below to register. For additional information, please contact Masahiro Tsuriya (firstname.lastname@example.org).
Session 1 (APAC)
Date: December 12, 2019
Time: 10:00 a.m. JST (Japan)
9:00 a.m. CST (China)
8:00 p.m. EST (U.S.) on Dec. 11
5:00 p.m. PST (U.S.) on Dec. 11
Session 2 (Americas and EMEA)
Date: December 12, 2019
Time: 7:00 a.m. EST (U.S.)
1:00 p.m. CET (Europe)
8:00 p.m. CST (China)
9:00 p.m. JST (Japan)
AIM Solder, a leading global manufacturer of solder assembly materials for the electronics industry, is pleased to announce its new NC259FPA Ultrafine No Clean Solder Paste, which it revealed recently during the Productronica Germany trade show.
Real Time with... productronica 2023: Koh Young Discusses Semiconductor and Advanced Packaging Inspection11/27/2023 | Real Time with...productronica
Koh Young’s Harald Eppinger talks about the company’s technology for the semiconductor and advanced packaging market and how they address the challenges introduced by reflective components and micro solder deposits.
HyRel Technologies Attains ITAR Registration, Reinforcing Leadership in Robotic Solder Component Tinning11/27/2023 | HyRel
HyRel Technologies, a global provider of quick turn semiconductor modification solutions, announces the achievement of International Traffic in Arms Regulations (ITAR) registration.
Mek (Marantz Electronics), a leader in Automated Optical Inspection (AOI) solutions, used last weeks’ Productronica show in Munich to proudly introduce the SpectorBOX X series, a modular full 3D AOI system for THT solder joints and THT components.
Productronica 2023 played host to the IPC World Hand Soldering Competition, bringing talented regional solder champions from all over the globe to compete for the title of World Champion. Each competitor was given sixty minutes to assemble a complex printed circuit board with their performance judged in accordance with IPC-A-610 Class 3 criteria. Each competitor’s efforts were rated on the merits of the results achieved, scored on the quality of the assembly process, the electrical functionality of the assembly and the speed at which the assembly was produced.