The Aerospace and Defense Chapter of the HIR

Estimated reading time: 2 minutes

Nolan Johnson and Andy Shaughnessy recently spoke with Jeff Demmin of Keysight Technologies, who breaks down the work his team has done on the Aerospace and Defense Chapter of the Heterogeneous Integration Roadmap (HIR).

Nolan Johnson: Jeff, IEEE pointed us in your direction to discuss your chapter of the HIR. What’s your background and involvement with the HIR?

Jeff Demmin: My background is broadly in semiconductor packaging. From 2015 to 2019, I worked for a company called Booz Allen Hamilton, which is a major government contractor. In that role, I supported leading-edge technical research related to packaging and heterogeneous integration, primarily at DARPA. I also have some background in the publishing world.

With my long career in packaging and my more recent experience specifically in the military and aerospace arena, I got tapped to work on the Aerospace and Defense Chapter of the HIR. I know most of the people involved in it, and I like to participate in industry activities, so it was an obvious match. Also, I want to be clear that my involvement is as the co-chair of this committee on the HIR and is not associated with my work for Keysight Technologies, nor does it represent the company’s thoughts. I do this mostly in my spare time, which is probably true of many of the people participating.

I jumped in relatively early a few years ago, shortly after the HIR effort was begun. It was created to continue the work of the broadly used International Technology Roadmap for Semiconductors (ITRS), which had been around for a couple of decades, driving the node-based metrics for how the semiconductor industry should move ahead. But with Moore’s Law running out of steam, mostly meaning that it’s too expensive to keep it going, the HIR was one thrust that arose from the demise of the ITRS.

Johnson: The rationale makes sense. There may be a portion of your overall design that requires cutting-edge fabrication technologies but forcing your entire design to adhere to that just because you need it in one key section has always been onerous. This does give you the opportunity to flex with what’s inside the package.

Demmin: The most obvious example of that, which has been recognized for a long time, is memory and processors. They use different fabrication processes. It’s still silicon, digital, etc., but they’re different processes just because of the nature of how they function. Splitting memory off from processors has been common for quite a while.

But all the other functions that end up in a big system-on-chip piece of silicon makes it quite inefficient to do it that way. Designers do everything they can to minimize the area’s silicon usage. And if you can carve out something that doesn’t need that leading node, that’s a smart thing to do, but you need to put it all back together after you carve it up. That’s the heterogeneous integration angle need that arises from this partitioning.

To read this entire interview, which appeared in the October issue of Design007 Magazine, click here.

To learn more, read Demmin's article "The Heterogeneous Integration Roadmap for Aerospace and Defense" in October's SMT007 Magazine.