Cadence Advances Radar, Lidar, Communications Processing for Automotive, Consumer and Industrial MarketsJuly 4, 2022 | Cadence Design Systems, Inc.
Estimated reading time: 2 minutes
Cadence Design Systems, Inc. expanded its popular Tensilica® ConnX family of radar, lidar and communications DSPs with the debut of two new DSP IP cores for embedded processing in the automotive, consumer and industrial markets. The small, low-power Cadence® Tensilica ConnX 110 and ConnX 120 DSPs share a common instruction set architecture (ISA) with the proven high-performance ConnX B10 and B20 DSPs, offering customers even greater design flexibility. Together, these four DSPs cover a broad performance range from the low to the ultra-high-end, delivering scalable best-in-class, power, performance and area (PPA). For more information, visit www.cadence.com/go/connx110.
The 128-bit ConnX 110 DSP and 256-bit ConnX 120 DSP feature an N-way programming model and are fully compatible with the ConnX B10 and B20 DSPs, preserving software compatibility for easy migration. Like the rest of the Tensilica DSP portfolio, the ConnX 110 and ConnX 120 DSPs support the Tensilica Instruction Extension (TIE) language, which allows customers to tailor the instruction set, add specialized data types, and implement tightly integrated interfaces between the DSP and external logic. In addition, the new DSPs are supported by a comprehensive set of complex math library functions in the NatureDSP, Eigen and Radar libraries. All ConnX DSPs are automotive-ready with full ISO 26262 compliance to ASIL-D with FlexLock or to ASIL-B.
The Tensilica ConnX 110 and 120 DSPs offer the following features and capabilities:
- Optimized instruction set for radar, lidar and communications applications
- 128-bit (ConnX 110) and 256-bit (ConnX 120) SIMD performance for complex math operations based on 8-, 16- and 32-bit fixed-point and half-, standard- and double-precision floating-point
- Common instruction set and simplified programming model, allowing code to be written once and utilized across different SIMD widths within the ConnX family
- Architecture optimized for small memory footprint and low-power signal processing
- Optional acceleration operations for linear-feedback shift, convolutional encoding, single peak search and dual peak search
- The ConnX 120 additionally offers Viterbi and Turbo decoders
“NXP continues to rely on the Cadence Tensilica DSP cores for our ADAS product offerings,” said Robert Dunnigan, director program management ADAS at NXP® Semiconductors. “We have several generations of radar products covering applications from simple corner radar to advanced front end and 4D imaging radar solutions that all utilize these DSP cores. We are looking forward to the advancements in feature set and performance improvements that the ConnX family of products will bring, as well as the continued focus on Automotive ASIL-B/D support as well as ISO 26262 compliance that Cadence provides with their DSP offerings.”
“indie is committed to developing multiple sensor modalities to enable safer vehicles in the pursuit of the uncrashable car,” said Lionel Federspiel, executive vice president of engineering for indie Semiconductor. “Cadence’s Tensilica ConnX processor family in conjunction with indie's architecture is ideally suited to implement unique design solutions with high performance, low power, and gate count optimization. As a pure-play automotive solutions innovator, quality and reliability are essential to the success of our products.”
“Radar and communications processing trends require solutions that perform more processing in less time,” said David Glasco, vice president of research and development for Tensilica IP at Cadence. “Automotive radar demands multi-antenna, high-resolution systems with rapid response. Similarly, 5G wireless communications requires much higher data rates and lower latencies than previous generations. The Tensilica ConnX 110 and ConnX 120 DSPs meet these demands by extending the already-efficient processing capability of the ConnX DSPs and enhancing them with even more fixed- and floating-point complex data processing capacity at low power and area.”
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