Manufacturing and Reliability Challenges With QFNs: Part II

Estimated reading time: 5 minutes

By Craig Hillman and Cheryl Tulkoff, DfR Solutions Inc.

One of the fastest growing package types in the electronics industry today is the quad flat pack no lead (QFN), also known as a bottom-termination SMT component. While the advantages of QFNs are well documented, concerns arise with manufacturability, compatibility with other OEM processes, and reliability. In Part I, we covered design for manufacturability (DfM) and introducing QFNs into products. In this section, we'll cover reliability of QFN components.

Acceptance of this package, especially in long-life, severe-environment, high-reliability applications, is currently limited. One of the most common drivers for reliability failures is inappropriate adoption of new technologies. This is especially true for new component packaging like QFN. Obtaining relevant information can be difficult since data often are segmented and the focus is on design opportunities not reliability risks. Most OEMs have little influence over component packaging; most devices offer only one or two packaging styles. Reliability testing performed by component manufacturers is driven by JEDEC (JESD22 series A & B) and the focus is almost entirely on die, packaging, and first-level interconnections (wire bond, solder bump, etc.) The only focus on second-level interconnect (solder joints) within JEDEC is the JESD22-B113 Cyclic Bend Test, which is driven by the cell phone industry.

There has been some attempt to rectify this absence of information through IPC-9701. Unfortunately, the results have been limited, as most component manufacturers are not interested in performing thermal cycling or vibration tests of second-level interconnects. This is either because their primary markets (consumer, computer) are not concerned with these stress environments or they view these issues as "application-specific," which can be translated as "this is your problem, not mine."

QFN Reliability IssuesReliability of a device is driven by the environment it is exposed to. For QFNs, concern arises under thermal cycling, mechanical cycling, and with the potential for dendritic growth.

Thermal cycling failures. Multiple package design changes have combined to increase the potential for solder joint failure in the current generation of electronic parts. The elimination of leads reduces overall joint compliance. As package sizes shrink, there is more silicon and less plastic, increasing the mismatch in the coefficients of thermal expansion (CTE) between the part and printed circuit board (PCB). Parts are running hotter, which increases the change in temperature (ΔT) at the joint.

The introduction of QFNs is part of this process of reduced robustness of second-level interconnects. For example, under standard thermal cycling environments, QFNs can experience an order of magnitude reduction in time to failure (TtF) from quad flat packs (QFPs) and a 3× reduction from ball grid arrays (BGAs).This is described in Table 1.

Figure 1. Failure as related to die/package ratios. Source: A. Syed and W.J. Kang, SMTA International 2003.

This reduction is driven by the die-to-package ratio, package size and I/O count, and the integrity of the thermal pad solder joint. In general, as die size, package size, and number of I/O increase, the number of cycles to fail will decrease sometimes quite dramatically. This can be seen in Figure 1, which demonstrates the sensitivity of time to failure as a function of die-to-package ratio.

Figure 2. Source: Wrightson, SMTA Pan Pacific 2007.

Thermal cycling takes on greater significance when QFNs are conformally coated. When coating material infiltrates under the QFN, the small standoff can result in a high stress state in the solder joint when the conformal coating expands during temperature cycling. Hamilton Sundstrand found a significant reduction in mean cycles to failure from a -55° to 125°C cycle, with uncoated QFNs failing in ~2,500 cycles and coated QFNs failing in as little as 300 cycles (Figure 2). A number of companies have responded to this by fencing off QFNs during the conformal coating process.

Figure 3. Source: International Rectifier, Application Note AN-1136.

Mechanical cycling. The low degree of lead compliance and relatively large footprint of QFNs can also result in issues during cyclic flexure events, such as bend cycling and vibration. For example, International Rectifier tested a 5 × 6 mm QFN to JEDEC JESD22-B113 (Figure 3). While the characteristic life demonstrated an extensive number of cycles to failure, the very low beta (~1) suggested brittle fracture, which could be an issue for certain environments. Unfortunately, very little test data or analysis is currently available to assess the robustness of QFN packages in these environments.

Dendritic growth. Large component area, multiple I/Os, and low standoff height can combine to trap flux under QFNs post-reflow. Processes using no-clean fluxes should be re-qualified, since particular design and process configurations could result in weak organic acid concentrations above a maximum (>150 µg/in2) desired level. Processes not using no-clean fluxes are vulnerable to dendrite growth without cleaning process modifications such as changes in water/solvent temperature, changes in use or style of saponifiers and surfactants, and changes to pressure and location impingement jets.

Figure 4. A 64-I/O Intersil package with strong separation of power and ground.

The electric field strength between adjacent conductors (voltage/distance) is also a strong driver for dendritic growth. Digital technology typically has a maximum field strength of 0.5 V/mil. Previous generation analog/power technology tended to limit field strength to 1.6 V/mil. The introduction of QFNs has increased these maximum electric field strengths, with some components having field strengths as high as 3.5 V/mil (Table 2). Some component manufacturers are aware of this issue and have modified their designs to maximize the distance between power and ground (Figure 4), while other manufacturers continue to have power and ground on adjacent pins.

QFN Risk MitigationTo create a path for the reliable introduction of QFN components in high-reliability/severe environment applications, designers, component engineers, and reliability personnel must be aware that heuristic rules may be insufficient and more comprehensive testing and analysis are required. These include establishing ownership of second-level interconnect, which can often be lacking; using test data and validated models to extrapolate the needed field reliability; reviewing existing processes, including post-reflow handling, coating, and rework; and considering mitigation strategies, such as bumping or reballing of QFNs, if necessary.

Craig Hillman and Cheryl Tulkoff, DfR Solutions Inc., may be contacted at chillman@dfrsolutions.com and ctulkoff@dfrsolutions.com, respectively. To read the first half of this two-part feature, go to Design, Manufacturing, and Reliability Challenges With QFNs.