Placement Quality Affects Costs

Estimated reading time: 10 minutes

Sjef van Gastel, Assembléon Netherlands B.V.

Each of the main SMT assembly processes has quality criteria that help determine the total process DPMO, which determines FPY. FPY determines the overall cost of placement. Perhaps the most significant practical impact on DPMO and yield is the placement technique, and in particular whether the machine uses parallel or sequential placement. Field data show that parallel placement can offer up to 30% better yields, based on DPMO numbers, than sequential placement. This article focuses on the major quality factors influencing SMT.

The main SMT assembly processes – stencil printing, pick-and-place, and reflow soldering – have each their own quality criteria. Each contributes to the total process defects per million opportunities (DPMO), which is the key parameter for an SMT placement line. That in turn determines the first pass yield (FPY), which is the key placement quality indicator for equipment manufacturers. More than anything else, the FPY determines the overall cost of placement. High FPY means low scrap and rework costs, and high return on investment (ROI).

Perhaps the most significant practical impact on DPMO and yield is the placement technique, and in particular whether the machine uses parallel or sequential placement. Field data show that parallel placement can offer DPMO rates of 10 DPMO or below, while typical rates for sequential placement are around 50 DPMO. That’s a yield difference of up to 30%. As a result, rework costs can be drastically reduced by using parallel placement.

Here, I focus on the major quality factors influencing SMT, outlining the DPMO and estimated yield calculation model defined in standard IPC-9261A, and discussing the relationship between placement machine concepts and placement quality control. I will examine practical DPMO and process yield results, and their relationship with SMT rework costs.

Typical SMT Flow Line

A typical SMT flow line has three major sections. Solder paste is applied using stencil printing and/or solder paste dispensing. Components are placed with placement machines, often using a mix of chip shooting, IC placement, and/or odd component placement. Then, solder is reflowed in a reflow oven. Although many companies still use wave soldering, this has more limitations for miniaturization, and I will only discuss reflow. Each of the three processes aims for zero defects to minimize rework and related costs.

Solder Paste Printing

The most common method of solder paste application is stencil printing. Here, a thin metal foil, e.g. the stencil, has small apertures coinciding with the corresponding footprint patterns on the substrate. This is used for transferring defined amounts of solder paste to the required shape and thickness. The paste is transferred from the stencil onto the substrate by a metal squeegee. The most important printing parameters are the stencil thickness, aperture geometry, squeegee geometry and speed, printing pressure, solder paste rheology, and stencil release speed. In essence, the solder paste printing process is all about applying the right amount of solder paste onto the right place on the substrate. There are three main defects from paste printing: pattern resolution issues, bridges caused by paste smears, and misalignment (Figure 1).

Figure 1. Misalignment at paste printing can lead to defects post-reflow.

Pattern resolution describes the shape of the solder paste deposits. Good quality deposits should have a flat surface on top, and a thickness equal to the stencil thickness. Bridging describes possible unwanted contact between neighboring solder paste deposits. Two neighboring deposits touching each other will initially lead to smearing and, after reflow, to solder bridging. Misalignment describes the positional offset of solder paste deposits with respect to solder lands. A small positional offset (< 25% of pad width) can be allowed, since this offset will be corrected by self alignment after reflow.

Sources of Placement Errors

The pick-and-place process should place the right components at the right positions on the substrate. Placement errors can lead to process errors after reflow. In this process, there are five important sources of placement error, most of which are caused by the pick-and-place machine.

Part misalignment will result in solder bridging or tombstoning after reflow. This can have multiple causes, including fiducial read errors, poorly calibrated machines, placement errors, component alignment errors, and parts sliding away from solder pads. Incorrect part selection will cause the wrong part to be mounted on the substrate. This is caused by wrong part feeder loading or tape splice errors. Damaged parts can lead to component cracking, as well as tilted components or open circuits. Parts are either damaged by the parts supplier, or in the pick-and-place machine from too high a placement force. Polarity-sensitive devices like diodes can be placed with the wrong polarity. This is caused by placement programming errors, or by incorrect tray loading where the tray has been rotated. Finally, there can be extra or missing parts. These are the result of parts gained or lost during pick-and-place actions.

Reflow Soldering

Reflow soldering is the final process step in SMT assembly, where the substrate and components are connected by the solder paste. The reflow oven has a certain conveyor speed and temperature profile, both for heating (until the solder paste reflows) and cooling (until the molten solder coagulates).

The peak temperature for lead-free soldering is around 280°C (235?240°C for tin/lead). First, the boards should heat up with a maximum temperature ramp of 3°C/sec. When the soak zone is reached, the flux agent becomes activated. When the oven reaches maximum temperature, it cools down at a maximum rate of 6°C/sec. It is the thermal mass of the components that largely decides the oven temperature profile. Large components with a high thermal mass will need more heat and more heating time than chips with a low thermal mass. A good compromise here is essential to avoid either cold joints for the large components or overheating and charring of the lesser chips.

Figure 2. Tombstoning is an important reflow-related defect, which can be caused by printing.

There are several possible types of reflow soldering defects. Tombstoning is caused by asymmetry in solder paste melting, causing one end of the component to rise. Bridging causes short circuits between a group of adjacent leads. Opens are when no joints are formed. Board warpage is a result of overheating. The formation of solder balls around a device is called solder beading, and is caused by an exaggerated capillary effect of paste moving under the component and squeezing out during reflow. Poor wetting causes poor solderability on tin/lead boards, although it is uncommon if the correct thickness of tin/lead solder is applied to the pad surface. Voiding is the formation of cavities in solder joints.

Note that some of these process errors in reflow soldering (including tombstoning, bridging, and opens) are caused in earlier stages of the SMT process. Tombstoning (Figure 2), for example, can occur as a result of part misalignment on the solder lands. In most cases, components will flow back to the center of the solder lands due to liquid solder’s surface tension. However, in extreme misalignments (component-to-land misalignment of above 25?50%), asymmetric solder paste deposits or asynchronous melting of the solder paste deposits will produce asymmetric forces. These can pull the component upwards to cause tombstoning.

IPC-A-610D and Quality Inspection Criteria

Quality inspection criteria for SMT assemblies can be found in the IPC-A-610D standards. To provide a common definition and understanding of process errors and so allow process quality results of different SMT flow lines to be compared, IPC established the IPC-9261A and IPC-7912A series of standards. These separate SMT defect opportunities into four classes. The first, component opportunities (Oc), means every part to be mounted onto the PCB (including the PCB itself) can be defective or damaged and counts for one component opportunity. The second, placement opportunities (Op), shows every part to be mounted onto the PCB (excluding the PCB itself) can be mounted wrongly (missing, misalignment, wrong polarity, and so on). Thirdly, termination opportunities (Ot) describe how every part to be mounted onto the PCB (excluding the PCB itself) can have wrong or missing contacts between the component terminations (bumps, leads) and corresponding solder lands. Finally, assembly opportunities (Oa) describe an overall defect opportunity that is not included in component, placement, or termination opportunity (conformal coating or cleaning). This defect opportunity class relates to the entire PCB assembly.

Figure 3. Relationship between defect opportunities, DPMO, and estimated yield.

A sample QFP, QFP48, will have a maximum defect opportunity of Oc=1, Op=1 and Ot=48. If SMT quality parameters go out of process acceptability limits, then opportunities become defects. Defects also fall into four classes. Component defects (Dc) describe every part mounted on the PCB (including the PCB itself) that is defective or damaged counts for one error opportunity. Placement defects (Dp) are for every part mounted on the PCB (excluding the PCB itself) that is mounted wrongly. Termination defects (Dt) related to every part mounted on the PCB (excluding the PCB itself) with wrong or missing contacts between the component terminations and corresponding solder lands. Assembly defects (Da) describe an overall assembly defect that is not captured within component, placement, or termination. Therefore, the maximum defect count for a QFP48 can be: Dc=1, Dp=1 and Dt=48.

DPMO and Estimated Yield

The DPMO index is defined as the number of defects divided by the number of defect opportunities, multiplied by 1,000,000. For a completed PCB assembly, the DPMO index is therefore:

The DPMO index is dominated by processes having higher opportunity counts (typically terminations). It may also be calculated for more than one PCB assembly by summing the defects and opportunities across all the PCB assemblies. An estimated yield can be calculated for a PCB assembly type to be run in a particular assembly process by using historical DPMO data from that process.

The estimated yield, Y=e-DPU, has an inverse exponential relationship to the defects per unit (DPU), which is the average number of defects per board (the average defect rate). So a DPU of 0.001 (1 defective board out of 1000 boards), would give a yield of 99.9%.

This defect rate must take into account all four defect classes. The defect rates for the classes may be numerically summed, since the opportunity counts for the individual classes are independent.

The relationship between the DPMO and the estimated yield is:

Using These Equations

Suppose a PCB assembly has a total of 1,000 components, including 800 0402-size capacitors. Then Oc = 800, Op = 800, and Ot = 1600 (800 capacitors with two terminations each). If there are also 100 0603-size resistors, then Oc = 100, Op = 100, and Ot = 200. With 70 SOT-23 package transistors Oc = 70, Op = 70, and Ot = 210 (this time, three terminations each). For 30 BGA-100 ICs Oc = 30, Op = 30, and Ot = 3000. The PCB assembly will be cleaned after reflow soldering, so Oa = 1.

The finished PCB assembly will then have Ototal = Oc + Op + Ot + Oa = (800 + 100 + 70 + 30 + 1) + (800 + 100 + 70 + 30) + (1600 + 200 + 210 + 3000) + 1 = 7,012.

Suppose the line cycle time for this PCB assembly is 40 seconds and there are 6,000 productive hours per year. Then, total number of defect opportunities per year are 540,000 × 7,012 = 3,786,480,000. If a total of 15,000 defects occur yearly, this will give a DPMO index of 15,000 ÷ 3,786,480,000 = 3.96, which can be rounded up to 4.

DPU will be 15,000 ÷ 540,000 = 0.0278 and so the yield = 97.26 %.

Figure 3 shows the relationship between the total number of defect opportunities for a PCB assembly and estimated yield as a function of the DPMO index. A lower DPMO index will increase the estimated yield and so reduce repair costs.

The number of defect opportunities per board depends on the number of components and the lead count per component placed on the board. The IPC international technology roadmap for electronic interconnections gives some statistics on board properties per end-product application (emulators). For example, the average component count for handheld electronics is between approximately 500 and 800 discretes and between 50 and 100 ICs. With an average number of leads per component of between 4 and 10, the total number of defect opportunities will vary between 3,300 and 10,800. With this defect opportunity window, Figure 3 shows that a DPMO of 20 or better is needed for an estimated yield of 80% and a DPMO of 10 or better to obtain an estimated yield of 90%. To obtain yield figures this high, it is necessary to control all the SMT process steps.SMT

Sjef van Gastel, manager of advanced development, Assembléon Netherlands B.V., may be contacted at sjef.van.gastel@philips.com.