New Acoustic Capabilities Aid Flip Chips

Estimated reading time: 6 minutes

In the past, flip chips have achieved higher I/O counts repeatedly to take advantage of their compact design. High-density flip chips with pin counts near 5,000 - a level that existed only in R&D experiments years ago - now are in production. Within a year, pin counts of 10,000 will be produced, with one estimate calling for flip-chip pin counts of 20,000 by the year 2010.

By Tom Adams

High pin count flip chips are usually found in high-end applications, and on inorganic substrates. One example of this is the pixel detectors at the Atlas project of the Large Hadron Collider under construction on the border of France and Switzerland. In this application, ICs having 3800 solder bumps at a 50-micron pitch are mounted face down onto the silicon sensor substrate. A number of these flip chips form an array that serves as the pixel detector. Because the array is intended to have a long service life and will be exposed to radiation, a flip-chip approach was selected over fragile wire bonds.

While flip chips are moving into numerous high-end applications, they are also moving into a significant number of low-end applications, such as consumer products. These products feature lower flip-chip material costs and higher overall productivity, which has made the move from wire-bonded ICs worthwhile.

Reliability Issues

A significant concern in all flip-chip applications is long-term reliability. The solder bump interconnects are hidden from view, precluding optical inspection, and cannot all be accessed for electrical inspection. Only a slight degree of process drift is needed to cause an eventual open or short as the result of minor variations during bumping, placement, reflow or underfilling. The Atlas project, for example, can tolerate I/O errors at a maximum level of 1 in 10,000.

Among high-end production of flip chip on substrate assemblies, 100% acoustic inspection by automated systems has become more or less standard because the reliability requirements are so high. High-throughput automated systems image the assemblies in JEDEC-style trays handled by automated equipment; the systems themselves are an integral part of the production line. The defects found by acoustic micro-imaging are typically voids or delaminations in the underfill, although less frequent defects such as disbanded bumps, partly bonded bumps, missing bumps and wrong-sized bumps also are imaged.

To perform acoustic micro-imaging of a flip chip, the ultrasonic transducer scans the top surface of the face-down chip - an advantage in imaging because the bulk silicon of the chip is both homogeneous and virtually transparent to ultrasound. The depths of interest lie between the die face and the substrate. Within these depths, ultrasound pulsed by the transducer sends back echoes that arrive at the transducer at slightly different intervals. The return echoes are typically gated to confine acoustic imaging to a specific depth of interest.

Common Imaging Approaches

A common imaging approach is to gate the echoes at two successive depths: first, the interface between the die face and the underfill (a depth that also includes the bonds between the solder bumps and the bond pads on the die), and secondly the interface between the bottom of the solder bumps and the substrate. In today’s flip chips, the total offset between the die face and substrate often is so small that the entire range can be gated, although more precise gating is useful in determining the precise depth of a feature.

Ultrasound pulsed by the transducer is reflected only by material interfaces within the flip chip. This is why the bulk of the chip itself is non-reflective. At a well-bonded interface, such as that between a solder bump and its pad, the degree of reflection depends on the acoustic impedance (density × acoustic velocity) of the two materials. The strongest reflections, and hence the brightest pixels, are produced by interfaces between a solid and a gas - or through gap-type defects such as delaminations, voids and cracks, which are standard threats to reliability in flip chips.

The development of acoustic imaging technology has paralleled advances in flip chips. Smaller solder bumps and finer pitches have required higher resolution in acoustic images; accordingly, transducer frequencies have moved progressively from 100 MHz to 180MHz, to 230 MHz and most recently to 300 MHz. The higher frequencies, which have smaller spot sizes and thus yield higher resolution, have been accompanied by increased sophistication in overall transducer design. At each frequency there are several available transducers, each with properties that give specific advantages in various types of imaging.

The reliability of acoustic imaging has also been enhanced by the recent release of a calibration wafer*, a 2" silicon wafer into which lines and dots of various dimensions have been etched. The wafer is bonded to a glass overlay, and the lines and dots lie at the interface between the silicon and the glass. Since the dimensions of the lines and dots are known, imaging these features gives the users of any acoustic micro-imaging system a tool for calibrating the system.

Figure 1. High-resolution acoustic image of a high-density flip chip having 1,296 solder bumps. Bright areas at the lower left are voids in the underfill.

Figure 1 and Figure 2 are the acoustic images of a flip chip having an array of 1296 solder bumps. The return echo signals were gated at the interface between the underfill material and the chip face. Two features stand out. First, all of the solder bump bonds (the gated interface images the bonds of the bumps to the pads on the chip) have the same medium-bright appearance that is consistent with successful bonding. The appearance of the solder bumps at this depth gives additional information as well. There are no gap-types defects between the chip and the bond pad, and none (such as cracks) within the chip itself. Although gaps in this region would likely be small and thin, their detection is aided by the fact that ultrasound is nearly 100% reflected, even by gaps with vertical dimension ranging from 100 to 1000Å.

Figure 2. Resolution of the high-frequency acoustic image permits magnification of fine details.

Secondly, there are two voids in the underfill material. Because they contain a gas (low density, low acoustic velocity), the voids are highly reflective and are the brightest features in the images. The larger void is at the lower left; the second, much smaller void is above it to the right. Voids are serious defects because they can create a space that solder could creep into. The smaller void points out one of the difficulties in advanced flip-chip production - in a fine pitch array, there is no location where even a small void is not dangerously close to a solder bump.

Five percent of the area of a flip chip has about 5,000 solder bumps (Figure 3). Gating, as shown in Figures 1 and 2, was on the interface between the die and the underfill. These several small bright areas could be described as voids or delaminations, but in any case they are gap-type defects that can impair the reliability of this advanced design. The bonds of the solder bumps to the die face, however, have a uniform appearance - a dark outer ring with a brighter center.

Figure 3. Acoustic image of a small region of a flip chip having about 5,000 solder bumps. White areas are voids or delaminations.

Figure 4 shows a non-array flip chip where the filler particles are unevenly distributed, probably as a result of phase separation during flow. The irregular lighter and darker areas are regions of lower and higher concentrations of filler particles - visible acoustically because each filler particle causes a tiny reflection of ultrasound. Uneven particle concentration often is associated with the formation of voids, and this portion of the chip has two voids (shown by the arrows). The void at the lower left is not near solder bumps, and may be small enough to have no significant impact on thermal management of the chip, but the void at the upper right surrounds three bumps and is very likely to cause an electrical failure.

Figure 4. Uneven particle distribution in the underfill of a flip chip. The bright areas are voids.

* Sonoscan, Inc.

Tom Adams, consultant, may be contacted at Sonoscan, Inc.; e-mail: info@sonoscan.com.