EIPC Summer Conference: Day 2July 2, 2015 | Pete Starkey, I-Connect007
Estimated reading time: 11 minutes
Refreshed after an excellent conference dinner, and for most, a good night’s sleep, delegates returned for the second day of the EIPC Summer Conference in Berlin, continuing the theme of improving profitability through technical leadership and innovation to meet future market requirements, with sessions on materials and processes for high performance PCBs and advanced material testing strategies to meet OEM and ODM needs.
The materials and processes session was moderated by Professor Martin Goosey, Vice President, Technology at EIPC, and his first speaker was Martyn Gaudion, MD of Polar Instruments with a presentation entitled “Fast and Fine: addressing the challenges of impedance measurement on fine line traces.” Beginning with his customary declaration that “All models are wrong, but some of them are useful,” and with reference to the differences between “lossless” and “lossy” transmission lines, he explained that fabricators building designs for frequencies below 2GHz typically worked on the basis of lossless characteristic impedance Zo, whereas in designs of 2GHz and above the focus shifted towards measurement of insertion loss in the transmission line. There was a grey area where lines operating at moderate speeds experienced low-frequency losses because of fine line geometries, and the correlation of measured impedance with modelled results was not as precise as would be expected. From a few MHz to 2GHz, losses were small enough to ignore, and impedance could appear the same at any point along the line. In fact, 100% of the signal energy was transmitted along the line and any losses were primarily the result of mismatch of input and output impedance causing reflections. From 2GHz upwards, losses in copper and dielectric absorbed power from the signal and, as frequency increased, proportionately less signal was transmitted. When attempting to make a measurement of the characteristic impedance of a fine line, these accumulated DC and AC resistances caused a slope on the TDR trace so that the observed value varied depending whereabouts on the trace it was measured. Launch point extrapolation was a method of computing the instantaneous or incident impedance by removing the DC and AC resistance effects, enabling better correlation between field solver modelled and actual measured values.
Dominique Garmy, from DuPont Circuit and Packaging Materials discussed flexible circuit materials for high-temperature environments, commenting that although an increasing number of automotive, military, aerospace, oil and gas applications required flexible circuits capable of withstanding high service temperatures, there had been a shortage of suitable materials and a lack of good test methods for evaluating and qualifying them. Failure mechanisms fell into three categories: adhesion loss, between copper and dielectric or between dielectric layers; embrittlement of dielectric; and embrittlement of copper. In most cases flexible circuit dielectrics were the first to fail, thermoset adhesives being more sensitive to embrittlement than polyimide films. One UL rating for high temperatures was based on relative thermal index (RTI), determined by loss of tensile strength and dielectric strength with long term thermal ageing. Samples were tested without copper so the test did not relate to any copper-adhesion loss and by itself was not a good measure of the capability of a copper clad laminate. The other UL test was maximum operating temperature (MOT), primarily determined by loss of copper adhesion after accelerated heat aging. The IPC service temperature test IPC-TM 2.6.21B appeared to work well for testing copper clad laminates but not as well for bondplies and coverlays. A new coverlay test, based on bend-testing, had been demonstrated, and overall results clearly indicated that all-polyimide clads, bondplies and coverlays provided the highest service temperature performance, with results close to industry experience. DuPont would continue to refine the new coverlay service temperature test and proposed to recommend its adoption by IPC.
Eric McLean, sales manager at Cambridge Nanotherm in the UK, discussed a nanoceramic dielectric designed to expand the performance of metal-in-board PCBs. Traditional metal-in-board substrates were limited in performance by the use of polymeric materials to provide electrical insulation and mechanical adhesion between the copper conductor layer and the aluminium core. These polymers had significant thermal resistance and a low degradation temperature which tended to restrict their continuous operating temperature to below 150°C.
McLean described an innovative electrolytic process for converting the surface of aluminium to a dense, strongly adherent, layer of nanoceramic, the dielectric properties of which were better than those of sintered alumina, such that only a 10 micron layer was required for electrical insulation. “It’s alumina, but not as you know it!” Since the nanoceramic material had good thermal conductivity, the thermal resistance of the coating, quoted as 0.014°C.cm2/W, was the lowest currently available. Direct metallisation of the nanoceramic eliminated all organic constituents in the construction and enabled sustained operation at temperatures above 250°C. Because the nanoceramic was formed by a self-levelling conversion process, through and blind vias could be straightforwardly coated, irrespective of aspect ratio, so that double-sided circuits could readily be fabricated. And the coating was capable of withstanding bending without cracking or peeling, so that substrates could be post-formed into three-dimensional shapes. Application examples included LED chip-on-board modules, LED light engines, power amplifiers and switching power supplies.
Hiroyoshi Tojima, from MEC Company in Japan, described how an anisotropic etching technology developed for chip-on-film applications was being adapted for HDI and packaging applications. In chip-on-film devices such as the drivers for LCD displays, 10 micron lines and spaces on 8 micron foil were typical and satisfactory definition was difficult to achieve by conventional subtractive techniques because of lateral attack by the etchant. Semi-additive techniques gave better conductor cross-section but were comparatively complex and higher in process cost. Physical limitations were the non-planarity of plated conductors and a tendency for undercut at the flash-etching stage to initiate peeling-off of fine conductor features. So there was a technical demand for an anisotropic subtractive process, to which MEC Company had responded by developing an additive for cupric chloride based etchant, which formed a protective film at the sidewall and inhibited lateral etching, giving a remarkable improvement in etch factor. Although etching machine set-up was critical and there was a narrow operating window, the process had established almost 100% market share with Japanese and Korean chip-on-film manufacturers. So it was logical to develop a variant of the process for HDI and packaging manufacture, where the line width demands were not as crucial but panel sizes were much larger and double-sided etching was required. Another complication was that the copper was likely built up in layers of material of different origin, for example: foil copper, catalyst, electroless copper, electroplated copper, all of which could have different etching characteristics. The target was to achieve an etch factor better than 4.0 on 40 micron lines and spaces in 18 micron copper. Extensive trials had been carried out over a wide range of operating parameters and circuit geometries, and it had been shown that the addition of only 5% of MEC’s proprietary additive in standard etching equipment achieved the target etch factor whilst reducing contact time by 10–15%.
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