The Shaughnessy Report: The Designer Roundtable Roundup

Estimated reading time: 2 minutes

Every year, I attend SMTA Atlanta, just across town. You have to love a local trade show! No airlines, no jet lag, and no hotels. It’s a small show; it would fit in a school gymnasium. 

Regional tabletop shows like this may be the next big thing. Fees for exhibiting are so low that it’s hard to justify not exhibiting. Some companies had their local reps manning the booths, but I talked to exhibitors who flew in from all over the East Coast, including one technologist from Canada. If you can tie in a few customer visits, the trip can pay for itself. 

But for me, the highpoint of SMTA Atlanta is the Designers Roundtable. This informal gathering usually draws about a dozen PCB designers, some of them ex-Scientific Atlanta veterans. It’s moderated by UPMG’s Pete Waddell, and we bounce questions off the designers for an hour or so. It’s very informal, and it draws many of the PCB designers in metro Atlanta.   

This year the roundtable had 15 attendees, up from 12 last year. Two of the new attendees were under 35, which surprised all of us. They design medical boards, which isn’t such a surprise; that’s one segment that keeps on growing. Most of the designers attending work for Cisco, Siemens, Sienna, NCR, and a few other smaller firms. 

A few takeways: None of these designers thought much of solder mask-defined pads, because they create more problems than they solve. 

• They don’t trust CAD vendors’ libraries, and there’s not much love for OEMs’ libraries either. One designer said he spends hours re-inventing the wheel designing footprints he’s used before. 

• They didn’t see much hope for the new “pay per use” license being floated by companies like ANSYS. One designer said that soon they’d all be back renting mainframe time like it was 1987 all over again. 

• As always, most designers at the roundtable have a love/hate relationship with their EDA tools. One Cadence user said he really loves his tool’s horsepower, but he’s glad Dal Tools makes Cadence tools work better.   

• None of these attending designers, or even their companies, use signal integrity or EMC simulation. One designer said, “All of the simulation in the chip is already done.” 

• Most of these designers don’t like updating their EDA tools because each new rev of the tool contains even more errors than the previous rev.  

To read this entire article, which appeared in the May 2016 issue of The PCB Design Magazine, click here.