Cadence Announces Industry’s First Verification IP for PHY Covering Multiple Protocols
February 26, 2020 | Business WireEstimated reading time: 1 minute
Cadence Design Systems, Inc. today announced the availability of the industry’s first Verification IP (VIP) for physical layer (PHY) verification. The Cadence® VIP for PHY covers multiple protocols and allows customers to thoroughly test and optimize their PHY designs, accelerating the development of data center, artificial intelligence (AI), machine learning (ML) and mobile application designs.
The Verification IP for PHY is part of the Cadence Verification Suite™ and supports the company’s Intelligent System Design™ strategy, enabling SoC design excellence through best-in-class IP. For more information on the Cadence PHY VIP, please visit www.cadence.com/go/PHYVIP.
The new Cadence VIP for PHY offers customers a comprehensive verification solution for the most complicated and challenging physical-layer interfaces and protocols, including PIPE 5.2 for PCI Express® (PCIe®) 5.0, USB3 and USB4, DFI for LPDDR4, DDR5 and HBM2E, and MIPI® D-PHY?/C-PHY? for CSI-2? 2.0 and DSI? 2.0. With the PHY VIP, customers can shorten time to market through advanced built-in capabilities for PHY verification such as:
- PHY-level timing checks
- Ability to drive protocol-aware and protocol-agnostic traffic for exhaustive testing
- A built-in scoreboard for analyzing receive path, transmit path and loopback
- Control over jitter, spread spectrum clock and bit error rate
Additionally, the solution includes Cadence TripleCheck™ technology, which provides users with a PHY-related verification plan that is linked to the specification as well as comprehensive coverage models and a test suite to ensure compliance with the interface specification.
“Our PHY team has successfully utilized Cadence VIP for verification of various protocols such as USB3 and PCIe 4.0, enabling us to quickly deliver unique and innovative designs for a broad range of applications,” said Realtek’s Vice President and Spokesman, Yee-Wei Huang. “With the complexity inherent in verifying PHY designs, Cadence VIP for PHY addresses a critical and challenging verification task and provides the speed and accuracy we need to help our customer’s time to market.”
“PHY verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” said Moshik Rubin, Verification IP product management group director, System and Verification Group at Cadence. “With the industry’s first dedicated VIP for PHY, we’re enabling our customers to verify their PHY designs effectively, ensuring the designs comply with the standard specification and meet application-specific performance metrics to provider the fastest path to IP verification closure.”
Suggested Items
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.