Seven Tips for Your Next Stackup Design

Estimated reading time: 4 minutes

If interconnects were transparent, the stackup in your board would just be about how many layers you would need to route all the connections between components. In fact, some test boards that are strictly testing continuity and isolation do exactly this. Each layer is a dense packing of narrow signal traces connecting an array of pogo pin pads on the top side to an array of connectors to an ATE on the bottom side.

But rarely do we have the luxury of designing a board just for connectivity. When interconnects are not transparent, we must engineer them to reduce the noise they can generate. This is where design for signal integrity, power integrity and EMC—collectively high-speed digital engineering—are so important.

 Seven Tips for Stackup
1. An important element in reducing the noise contributions from the interconnects comes from the stackup of the board and the layer assignments. The very first step is to engineer all signal layers with at least one adjacent plane as the return path. This will reduce the crosstalk between the signal-return paths: the microstrip traces on the outer layers and stripline traces on the inner layers.

2. The striplines can be either one signal layer between two planes or two signal layers between two planes. With two signal layers between two planes, there is the danger of excessive crosstalk if signals on adjacent layers are routed broadside to each other.

3. To avoid this problem, it is best to route the adjacent signal layers in dual stripline stackups orthogonally. One signal layer is routed in the x-direction, the other in the y-direction.

4. When interconnects must distribute 10 A of current or less, traces as wide as 200 mils can carry the 10 A of current in 1 oz copper with an acceptable temperature rise. But, with larger currents, like 20 A or more, it may be necessary to use wide planes to distribute the current from the power generators to the power consumers on a board. This is when some of the planes should be allocated as dedicated power planes.

The challenge is balancing the requirements of power distribution with the requirements for reduced crosstalk from signals changing return planes.

In principle, a signal line will see exactly the same characteristic impedance if the return plane is at ground potential or 12 V potential or anywhere in between. The problem with using a different voltage plane than ground to carry return current is when the signals change layers.

5. When a signal trace switches layers, we use a via to carry the signal current. If the return plane also changes, we will achieve the lowest crosstalk between all the signals switching layers when we also provide a via to carry the return current from the starting plane(s) to the final plane(s). This is a lowimpedance via shorting between the two different return planes. This is only possible if the return planes are the same voltage. If they are at different voltages, we can’t add a shorting via between them. This is a strong motivation to only use ground planes as the return planes for signals.

6. At best, if the two planes are a different voltage, we can add shorting vias between the two planes with a DC blocking capacitor between them. The loop inductance through a DC blocking capacitor can be as much as 5x higher impedance of a direct shorting via. It is a poor approximation to a shorting via, but the best we can do.

7. When signals change return planes and the planes are at different voltages, we run the risk of launching high bandwidth return currents into the cavity formed by the two planes. This is a source of long-range crosstalk and potentially a source of radiated emissions noise. One solution to reduce the noise in the power-ground cavity is by using very thin dielectric in these layers. This suggests that when power planes are used, they should be paired with closely spaced adjacent ground planes.

Once the order of the signal layers and planes is set, the dimensions can be calculated based on the line width of signal traces, the dielectric constant of the laminates used, and the target single-ended or differential impedance. This is where a 2D field solver comes in handy to define the cross section of microstrip traces, single layer stripline and dual layer strip line traces.

If you don’t follow these tips, it does not mean your board will not work. Unfortunately, there is no way of knowing if your stackup design will work or not unless you do a detailed analysis based on the driver models and 3D electromagnetic analysis of all the worst-case signal and power paths. Implementing these tips is about risk reduction.

They are part of a balanced diet of best stackup design practices, best signal routing design practices, and best power distribution design practices. And like all design guidelines, buyer beware. Always consider the best design practices, but also always do your own analysis.

This article appeared in the January 2021 issue of Design007 Magazine.