New Methods for Quantifying PCB Design Weaknesses and Manufacturing Challenges

Estimated reading time: 3 minutes

Nolan Johnson recently spoke with Summit Interconnect’s Gerry Partida about disruptive new methods for analyzing and quantifying potential manufacturing challenges in designs while still in the design phase.

Nolan Johnson: Gerry, what’s the background for the new methods we’re about to discuss?

Gerry Partida: The industry is at a new point in evolving how we look at building boards. Our industry has historically built boards and then tried to find a test for them. Then, when they found a test for it, they figured out that it needed to be analyzed before they built the board. We did this with electrical test. We built boards and down the road, as people started asking, “Why am I buying bad boards? We should electrically test them,” electrical test was introduced, reluctantly, into the test part of manufacturing printed circuit boards by suppliers or fabricators. Then they embraced it. But when we started testing boards, we did comparison tests. We would build a bunch of boards, put the first one on a tester, tell it to self-learn, and compare all the boards to the first board. If they all matched, they all shipped as matched boards, but if they had the same defect, they all shipped with the same defect. This did happen.

It wasn’t for another 10 or 15 years that we took extracted netlist from the CAD software and compared it to the Gerber data that would be used to fabricate the board, to find out whether everything was corrected before we started manufacturing. We would find that there was a problem, and we would fix it or get new data. Then when we knew we had a match, we started to manufacture the boards and downloaded the program to the tester. But this was an evolution of about 15 to 25 years. It depends on what point of view you take from it.

We’ve done the same thing with microvias. We’ve been building microvias. There are datasheets that talk about the modulus and the CTE expansion after reflow, before Tg, and after Tg, but no one really would do any math or science behind it. The PCB fabricator would just build the boards and ship them. Sometimes there are assembly problems, and the industry says, “There’s something going on with microvias. Three-stack and four-stack are not as safe as a single microvia and staggering them.” Everybody is trying to find out how strong or how weak they are. Most people were finding out at assembly because the standard IPC-6012 performance specs in the evaluation couldn’t identify a weak microvia very well. So, we came up with the OM tester, which is using the IPC-TM 650 2.6.27 test method, which actually takes a coupon with the same structures that are in the board and simulates reflow on the coupon before we ship the boards.

If that structure, which is in the board that we’re trying to ship, can survive reflow in a tester, then we know that the boards are more than likely going to pass and survive reflow and assembly. This works great. It will tell fabricators that if we process everything right, the board is going to be reliable through reflow. However, after a couple years of having the tester, we discovered we did everything right, but occasionally it wasn’t working. They were failing 6X reflow. Utilizing our extensive experience in microvia fabrication, our portfolio of reliability testing data, materials expertise and software tools, we can simulate the stack-up; you can actually input the microvia structure and the data output will tell you if it can survive six reflows or not.

To read this entire conversation, which appeared in the November 2021 issue of PCB007 Magazine, click here.