Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design
December 1, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.
Testimonial
"Our marketing partnership with I-Connect007 is already delivering. Just a day after our press release went live, we received a direct inquiry about our updated products!"
Rachael Temple - AlltematedSuggested Items
UHDI Fundamentals: UHDI Technology and Industry 4.0
09/03/2025 | Anaya Vardya, American Standard CircuitsUltra high density interconnect (UHDI) technology is rapidly transforming how smart systems are designed and deployed in the context of Industry 4.0. With its capacity to support highly miniaturized, high-performance, and densely packed electronics, UHDI is a critical enabler of the smart, connected, and automated industrial future. Here, I’ll explore the synergy between UHDI and Industry 4.0 technologies, highlighting applications, benefits, and future directions.
Pentalogix Launches ViewMate Essentials to Ensure PCB Designs are Manufacturing-Ready
09/03/2025 | PentaLogixPentalogix, Inc., a leader in PCB design solutions, announced the launch of ViewMate Essentials, an advanced CAM package designed to enhance the workflow of PCB designers. Available starting September 2nd, 2025, ViewMate Essentials enables designers to view, edit, and manage PCB manufacturing files with exceptional precision, facilitating seamless collaboration with PCB fabricators and assemblers.
The Global Electronics Association Launches Design Village at APEX EXPO 2026
09/02/2025 | Global Electronics AssociationAPEX EXPO, the hallmark electronics tradeshow hosted by the Global Electronics Association, announced the launch of the Design Village, a new feature in the exhibit hall that will unite the world’s leading innovators and showcase next-generation solutions for the electronics industry.
Connect the Dots: How to Avoid Five Common Causes of Board Failure
09/03/2025 | Matt Stevenson -- Column: Connect the DotsBoards fail for various reasons, and because I’ve been part of the PCB industry for a long time, I’ve seen most of the reasons for failure. As part of my ongoing crusade to help designers design for the reality of manufacturing, here are five common causes for board failure and how to avoid them.
Mastering PCB Floor Planning
08/28/2025 | Stephen V. Chavez, Siemens EDAPlacement of PCB components is far more than just fitting components onto a board. It’s a strategic and critical foundational step, often called “floor planning,” that profoundly impacts the board’s performance, reliability, manufacturability, and cost. Floor planning ties into the solvability perspective, with performance and manufacturability being the other two competing perspectives for addressing and achieving success in PCB design.