SMTAI Conference Preview: Paper Abstracts and Times

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SAN DIEGO — SMTA International (SMTAI) will hold its conference October 4 through 8 in San Diego, and the SMTAI Technical Committee reviewed more abstracts than any time in the past 5 years. The final selection consists of 120 papers with 18 short courses, as well as AIMS co-location, Emerging Technologies, the Lead-Free Symposium, the Contract Manufacturing Symposium, and a special keynote speaker from Jet Propulsion Labs. Following are some paper presentation highlights.

Some of the papers to be presented:Jim D. Raby, P.E., Mark McMeen, VP of engineering  services; and Casey H. Cooper, electrical engineering manager, STI Electronics Inc., will present “Imbedded Die Assembly Process, Is It Ready Yet?” during session ET3, “System in Packaging (SiP), Monday, October 5, 2009 from 1:00 to 2:30 p.m. in the California room. Various technologies for system and module miniaturization attracted increasing interest and gained process maturity recently. Depending on the application scenario, the technology of choice can be advanced chip stacking using silicon through via (TSV) technology or direct single or multiple chip embedding into the PCB. Examples of both will be covered in the SiP session. Current design problems are not driven by circuit design capabilities, but by an inability to reliably package these circuits within size and weight requirements outlined by the system-level specifications. Innovative packaging techniques are required to meet increasing size, weight, power and reliability requirements without sacrificing electrical, mechanical, or thermal performance. Imbedding components within organic substrates has been proven to meet these requirements. Imbedded Component/Die Technology (IC/DT) involves imbedding both active and passives into cavities within a multilayer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. This paper discusses the design methodology and validation/test data gathered during the implementation of IC/DT in a mixed-signal prototype. The prototype designed and assembled using IC/DT processes was subjected to reliability testing and ultimately demonstrated in a test flight. The results from this testing as well as the future designs utilizing IC/DT are presented.

Ravi Parthasarathy, senior process engineer, ZESTRON America, will present “Why Switch from Pure DI-water to Chemistry,” Tuesday, October 6 from 10:00 to 11:30am. Parthasarathy will discuss the challenges of DI-water cleaning processes and the limitations the North American market is facing while cleaning with pure DI-water. He will address the importance and necessity of chemistry-assisted cleaning especially when cleaning lead-free solder pastes and non-water-soluble residues. The latter are much more difficult to remove. Furthermore, cleaning of water-soluble fluxes in tight spaces is becoming more challenging with DI-water only. Its high surface tension (over 70 dynes/cm) makes it almost impossible to clean effectively under low-standoff components. The presentation will demonstrate the value-added benefits of chemistry-based cleaning processes, such as decreasing the overall process cost, better bonding and coating after cleaning, lower application temperatures, and wider process windows.

Mike Bixenman, CTO, Kyzen; Ning-Cheng Lee, Ph.D., Indium Corporation; and Steve Stach, Austin American Corporation, will hold “Ionic Cleanliness Testing Research of Printed Wiring Boards for Purposes of Process Control” during session SMT1, “Cleaning and Cleanliness Testing Challenges in a Lead-Free World,” Tuesday, October 6 from 10 to 11:30 a.m. Ionic Cleanliness testing machines are designed to determine the total ionic content extractable from the PWB, for process control. The conductivity of the extract solution is measured and results expressed as sodium chloride equivalence per unit area. The problem with this method is twofold: many of today’s low residue flux and lead-free flux residues are not soluble in the extract solution and contamination is with site-specific components, from which contamination does not correlate to the area of concern. The purpose of this study is to research low residue and lead-free flux structures, identify solvent compositions that will dissolve these residue types, and offer options for performing bulk and site-specific ionic cleanliness testing methods. This session will explore cleaning chemistries, flux chemistries, and cleanliness testing chemistries to provide insight into current technologies and what work is still needed in critical cleaning and cleanliness testing.

Chris Rockwell, director of sales – Americas, CyberOptics Corporation (NASDAQ: CYBE), will participate in the SMTA International exhibit floor panel discussions, organized by Global SMT & Packaging Magazine, “The Changing Face of Inspection,” Tuesday, October 6 from noon to 1 p.m. on the show floor. Predictive testing is the goal for many test-related companies. Recent innovations from manufacturers of printers and pick-and-place equipment are bringing inspection inside the box. The panel will discuss the merits of this development and whether it is a genuine step on the road to predictive testing. Rockwell holds a BS in electrical engineering and has worked at CyberOptics for 19 years.

Vitronics Soltec engineers Denis Barbini, Ph.D., and Ursula Marquez de Tino, Ph.D., will present “Characterizing Alternative Alloys for SMT Assembly” along with Brian Roggeman, UNOVIS Solutions during session MFX2, Tuesday, October 6 from 1:30 to 3:00 p.m.

David Bernard, Ph.D., product manager X-ray systems, Dage Precision Industries, a Nordson company (NASDAQ: NDSN), will present “The Challenges of Package-on-package (PoP) Devices during Assembly and Inspection.”  In his role, Bernard has gained worldwide recognition for demonstrating, training and problem-solving using X-ray inspection systems throughout the electronics assembly industry.  Bernard will be joined by international consultant Bob Willis, a lead-free auditor and workshop instructor. This technical paper outlines the processes associated with soldering stacked packages using dip flux and dip solder paste that are specifically designed to overcome the incidence of package warpage.  Based on real-world process issues, inspection results will be presented to better illustrate the challenges in implementing stacked packages into production. Bernard will also staff the Dage booth offering free and unbiased technical advice to help visitors with process problems and field failure analysis. Visitors are encouraged to bring their board assemblies for discussion and review as well as real-world, live examination to better understand the process problem and suggested solutions.  

Mike Bixenman, CTO, Kyzen; along with co-author Mike Konrad, president of Aqueous Technologies, will present “Cleaning for Reliability Post QFN Rework” during session SMT4, “Challenges and Solutions Relating to the Rework of QFN (Quad Flat No-Lead) Packages,” Wednesday, October 7 from 8 to 9:30 a.m. The need for cleanliness under individual components increases as the spacing between connector leads decreases and power increases. The low standoff height of QFNs traps flux between the ground pad and component leads. Entrapped flux under the QFN is a reliability concern. The purpose of this presentation is to make an argument for removing the residue under the QFN post-rework and present cleaning process options for meeting this cleaning challenge. QFN perimeter leads are located on the bottom of the package and a center thermal pad provides an efficient heat transfer path when soldered to the PCB. This package type was introduced specifically for applications where size, weight, and thermal and electrical performance is important. The QFN, however, presents some technical challenges, specifically in a lead-free environment, due to its unique structure and low standoff. This session will highlight some of these challenges, specifically relating to the rework process and post-rework cleaning.

FINETECH’s Neil O’Brien will present “Fine-pitch QFN Rework — Triple the Challenge in a Lead-free World” during session SMT4, “Challenges and Solutions Relating to the Rework of QFN Packages,” Wednesday, October 7 from 8 to 9:30 a.m. Quad flat no-lead (QFN) packages have gained acceptance and typically appear in densely populated boards where real estate is at a premium. As with all components, size and pitch continue to narrow, leaving traditional hand rework behind. The design, size, and assembly process of QFNs present unique rework challenges not seen with other components. The presentation will focus on the complete rework process, including component removal, site preparation, component paste printing, and finally new component soldering. The stencil design and paste process will be looked at in depth and soldering results evaluated. Triple row QFNs will be the test case.

Michelle Ogihara, sales and marketing manager, Seika Machinery Inc., will co-chair “Using Automated Inspection to Reduce Cost through Process Capability and Control” during session PRC1, Wednesday, October 7 from 8 to 9:30 a.m. in Royal Palms 1-2. Kazuo Kawai, SMT Consultant for Hirox-USA and Seika Machinery, also will present a joint paper titled “Inspection to Improve Lead-free Solder Technologies” during session PRC1. Having capable and controllable assembly processes are essential elements that characterize successful electronics manufacturing companies. High production yields result in low labor and scrap costs. An assembly infrastructure that takes advantage of today’s automated inspection technologies helps achieve best-in-class yields and significantly reduce labor costs associated with manual inspection. The key to process control is not to use these automated inspection tools reactively, but proactively in real time — identifying a process trending toward an upper or lower specification limit, not waiting until a process goes out of control. Micro packages such 0201s and 01005s, lead-free solder, BGAs, and other under-package I/O components all have confounded the inspection challenge. The papers in this session will document work that has been done to help meet these challenges.

Brian O’Leary, Americas sales manager and Mike Limberg, service tech, KIC, will present “7 Ways to Profile Profitability” during the free session, “Reflow Soldering Best Practices for Profiling and Optimizing,” Wednesday, October 7 from 10 to 11:30 a.m. in Garden Salon 1. Understanding the thermal reflow process has been a subjective event backed by limited data; however, experience and advances in the ability to collect data and deliver the data in a graphical and meaningful manner have lead to significant insights into the reflow process. KIC has found that a set of “best practices” that lead to more robust accurate profiles and lay the foundation for predictive modeling that can lead to host of cost savings and quality benefits to a SMT process. After the 30-minute session, KIC will be distributing a newly released book on profiling, full of tips and examples on how to improve a company’s process to session attendees.

Christian Ott, senior sales and project manager, SEHO Systems GmbH, will present “Effects of an Appropriate PCB Layout and Soldering Nozzle Design on Quality and Cost Structure in Selective Soldering Processes” during session SMT5, “Process and Design Optimization for Selective Soldering,” Wednesday, October 7 from 10:00 to 11:30 a.m. Selective soldering has been widely implemented in recent years, with a significant learning curve during its implementation ramp. This session highlights key process optimization results, design for manufacturing guidelines and techniques, and best process practices for transitioning from low- to high-temperature solders. Manual repair soldering that is expensive and time-consuming is already unacceptable due to the required quality and the reproducibility of the whole manufacturing process. In more than 80% of cases, solder bridges are the main reason for faults. The solder’s pull-off behavior is mainly responsible for a bridge-free soldering result in the selective soldering process. With many practical examples, the paper provides a detailed explanation of the individual points that should be found in the selective soldering process with regard to the assembly design and solder nozzle technology. The options for faultless and cost-effective electronic production will be shown step by step.

Denis Barbini, Ph.D.; Ursula Marquez de Tino, Ph.D.; and Jon Silin, Vitronics Soltec, will present “Developing the Optimum Reflow Process: a Matter of Cost and Quality” during session SMT6, Wednesday, October 7 from 1:30 to 3:00 p.m.

Greg Bannick, director of medical solutions, Kimball Electronics Group Inc., a subsidiary of Kimball International Inc. (NASDAQ: KBALB), will present “Overcoming Repair Depot Challenges,” during the Contract Manufacturing Symposium, Wednesday, October 7 from 1:30 tp 3 p.m. in Royal Palms 1-2, as part of a three speaker session focused on “Business Opportunities in Electronics Manufacturing.” Many OEMs develop a repair depot strategy reactively. Properly planned, repair depot services can be a source of customer satisfaction and even an additional revenue stream. Repot depots often also have the advantage of product lifecycles more aligned with component lifecycles, which minimizes the requirement to support obsolete product. Bannick will discuss the key issues that should be considered in developing a robust outsourced repair depot, including best logistics strategy, product support feasibility and challenges, environmental considerations, and supplier ability to support an evolving partnership. Bannick has over 26 years of experience in the EMS industry, specializing in the medical sector.

Mark J. Walz, founder, Training and Tooling Associates (T&Ta), along with co-author Michael Berry from Celestica, will present “Thru Hole Connector Rework Using Convection Heating” during session MFX3, “Connector Technology,” Thursday, October 8 from 3:30 to 5 p.m. in Royal Palms 3-4. Increasing customer requirements for performance, density, and reliability are creating challenges for SMT area-array and thru-hole connectors. This session will address SMT area-array design considerations, connector solder attachment methods, and thru-hole connector rework technologies. Reworking plated through-hole (PTH) connectors is more difficult with lead-free solders. Typical solder fountain connector rework has introduced a high incidence of specific defects, including copper dissolution and barrel cracking. A new method for connector rework uses convection heating for connector removal and automated vacuum solder scavenging to remove residual solder from the barrels. This paper discusses how convection heating on a Summit rework system has been improved by a bottom area heater, a bottom rectilinear localized heater, and a top heating nozzle. Vacuum scavenging is performed with software that uses a pre-programmed, automatic reciprocating pattern to draw solder from each barrel. Test results are obtained by the use of nitrogen gas for top heating during vacuum scavenging.

See more SMTAI news and product previews:Assessing Harsh Environments: SMTAI Keynote from JPL SMTA International Preview SMTAI Products Preview I SMTAI Exhibitor Preview II

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