-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueComing to Terms With AI
In this issue, we examine the profound effect artificial intelligence and machine learning are having on manufacturing and business processes. We follow technology, innovation, and money as automation becomes the new key indicator of growth in our industry.
Box Build
One trend is to add box build and final assembly to your product offering. In this issue, we explore the opportunities and risks of adding system assembly to your service portfolio.
IPC APEX EXPO 2024 Pre-show
This month’s issue devotes its pages to a comprehensive preview of the IPC APEX EXPO 2024 event. Whether your role is technical or business, if you're new-to-the-industry or seasoned veteran, you'll find value throughout this program.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - smt007 Magazine
Wafer-level Processing: Whose Job Is It, Anyway?
August 10, 2004 |Estimated reading time: 8 minutes
By Jody Mahaffey, JDM Resources
Santa Clara, Calif. — One of the hottest topics at SEMICON West in San Jose this year was wafer-level processing. Walking around the show floor, it was hard to find a wire bonder, but wafer bumping equipment and materials were everywhere.
SEMI even hosted an executive panel discussion on "Wafer Bumping Technology Strategies and Status," where it was reported that today, less than 5 percent of all die are being bumped, but in the next two to three years it is estimated that 20 to 30 percent of all die will be bumped at the wafer level. This increased interest and expertise brings us that much closer to true wafer-level packaging (WLP), which offers advantages such as smaller footprint and increased performance for higher speeds and increased functionality in portable devices.
As wafer-level processing and package assembly continue to converge and the lines between the front and back ends blur, many questions arise. One of the most important questions is, "Where will wafer-level packaging take place?" That is among the topics of the next Microelectronics Packaging and Test Engineering Council (MEPTEC) one-day technical symposium on August 19 in Santa Clara, Calif. MEPTEC will bring together experts from various areas of the WLP/processing fields to help answer that and other questions related to WLP.
Some speakers from the upcoming conference offered their insights regarding the ongoing discussion. When asked what part of the supply chain is responsible for WLP production, almost everyone has their own answer. Many people, like Bill Chen of ASE, agree that ultimately it should be a collaborative effort. Chen, a session chair for the symposium, believes, "Wafer-level packaging has been established as an effective and low-cost technology for IC packaging and assembly. In wafer-level packaging, the traditional boundaries between wafer foundry and IC assembly, and between IC assembly and electronic assembly are becoming blurred.
Exploiting the full potential of wafer-level packaging will require close collaboration and cooperation across the entire supply chain of the industry. Today, wafer-level package technologies are being exploited both at the IDMs as well as at SAT service providers. The history of our dynamic industry has shown that as with any new technology, there will not be one solution, but multiple solutions; be it SAT service providers, IDMs, wafer foundries or specialty companies. Wafer-level packaging will not be an exception."
Carl Buck of Aehr Test, a panelist in the Test Session of the symposium, agrees, adding, "Technologies to make WLP are being developed at semiconductor companies, packaging subcontractors and new companies, who are all inventing new packaging and interconnect technologies. If packaging subcons want to keep their place in the value chain, they need to lead the way!"
Many others believe that WLP belongs in the front end. Tom Di Stefano of Centipede Systems is also a session chair at the symposium. He says, "Although initial production and low-value parts will be contracted to packaging houses, most of the high value wafer-level packaging will be done by IC manufacturers. Many of the benefits of the wafer-level paradigm derive from better integration of the packaging function to achieve lower test costs, faster time-to-market and better logistics. To derive full benefit, the IC manufacturers will need to tightly integrate wafer-level packaging into their flow."
And then there are those like session panelist David Hays of Unitive, who believe that, primarily due to processing differences, WLP is the responsibility of packaging subcons who have integrated bumping capabilities. "Technologies required for bumping are in some ways equal and in other ways different, from those found in wafer fabs. Photolithography, resist processing, etching and electroplating all are now common in leading-edge fabs; however, the key difference is the thickness of these materials and the integration challenges and throughput hits, which occur in packaging due to the need for thicker materials. No fab manager in the world will commit a $20 million stepper to the type of resist processing necessary for packaging due to extremely low throughputs."Hays is quick to point out that processing differences are not the only issues that will keep WLP at assembly subcontractors. "You also have customers wanting a single point of contact to take responsibility for packaging activities. This results in a simplified (thus more cost-effective) supply chain.
But perhaps the most important issue is technology. As we drive to reduce pitch, eliminate lead, increase power handling and minimize size, extensive development activities are required to develop new technologies. The front-end fab guys already have their hands full developing processes: Cu, low-k, high-k, deep UV, etc. To now add additional costs in the form of people and equipment, when other companies are already offering the required packaging solutions, simply doesn't make economic sense. With so many other technology and competitive challenges being faced by the IDMs, they have to decide: do I put my cash into making my $1.5 billion fab productive with high yields, or invest in developing a bumping capability, which I can readily acquire on the open market?"Regardless of who builds the packages, there still are some technical barriers to be addressed if WLP is to move into mainstream applications. Both Di Stefano and Buck agree that advances in parametric test as well as functional test and burn-in are needed in order to extend the technology to higher-value devices.
According to Buck, "The basic problem is that WLP devices do not have standard sizes or pad locations, which is what test fixturing for standard packaged devices depends on. In addition, the pad pitches and sizes are smaller than can be handled by test fixturing for standard packaged devices. Solutions such as bare die carriers are available for this now, and full-speed and full-wafer test and burn-in are starting to be used."
Hays believes that new equipment enabling more efficient use of capital and new materials, such as those enabling larger die to be bumped without requiring underfill, are helping to eliminate technical barriers. Chen says, "To become mainstream, there must be efficient, cost-effective, high-volume manufacturing infrastructure, including wafer probe and final test in place. There must be continued R&D development in design, materials, processes and equipment as well as end market applications to feed into the pipeline. There will be many technical roadblocks and hurdles. But nobody expects it otherwise."
Besides technical barriers, there also are some market barriers holding WLP back. As usual, cost is at the forefront. Says Buck, "So far, WLP is typically more expensive than standard packaging, which goes against the continuous downward trend in the cost of electronic devices." Hays adds, "Cost of WLP has been an issue. For flip chip in package, the substrate cost is the No. 1 inhibitor to increased market uptake. Wafer-level chip scale package (WLCSP) avoids this dilemma, but is constrained due to die size limitations. As WLCSP technology advances, permitting larger die to be placed without the need for underfill, costs will decline and market acceptance will accelerate."
Both agree that some of these cost constraints may be overridden as consumers are willing to pay more for increased functionality, as seen in the cell phone market. Hays adds, "If a WLCSP costs a bit more, but allows the cell phone maker to add a highly desirable new functionality, like GPS, to his new product, his ability to capture early market share more than pays for the slight added cost of a WLCSP vs. other larger package types."
WLP cost issues go beyond increased package costs. Chen points out that substantial capital investment and technical resources will also be necessary. Another issue ultimately affecting cost is a lack of standards. As Di Stefano explains, "The single largest impediment to wide acceptance of wafer-level packages is standards — standards for the package as well as for handling, attachment, testing protocols and design. Without standards, companies cannot build an efficient infrastructure."
So once it is determined who is going to build wafer-level packages and technical and cost barriers are broken, the next question is: What applications are best suited for WLP? Most everyone agrees that RF/wireless devices for portable products are an ideal fit. Di Stefano expands on that, saying, "Next, I expect memory devices to take off, as soon as reliable interconnect attachment technology is accepted as standard. Processors and ASICS have the most promise, but these applications require advances that are years off. Looking further into the future, WLP will pervade all IC production because of the cost, logistics and functional imperatives."
Hays agrees that, "Memory will become key in the next year as packaging technologies evolve to support larger die without the need for underfill," adding, "Stacked die and SiP package types are a perfect fit for WLP."
Chen sees WLP conversion in a broader sense, saying, "WLP is and will continue to develop and evolve in different directions and into many forms. Some will become mainstream, some others will stay as a niche technology in a specific market application, while others will fade away."
Ultimately, the goal of the MEPTEC conference is to bring together different sectors of the supply chain to address these issues and others. Chen, session chair for the Strategies for Industry Collaboration session, feels this symposium is a great opportunity for all sectors to discuss the issues together. "The key to WLP is to provide low-cost and efficient packaging solutions to end customers. This will involve significant investment in high-volume manufacturing infrastructure and advanced technology, as well as collaboration with the foundry and EMS companies in the supply chain towards delivery of the best low-cost and effective packaging solutions to the end customers.
WLP will happen when all sectors of the industry work together to provide cost-effective solutions to customer's applications. This is what is happening today and is the main reason that WLP has been propelled into mainstream."
Nick Leonardi, Symposium co-chairman and president of TechDirect Consulting Services, is excited about the program and speakers, saying, "We are pleased to be able to bring together WLP industry experts in the areas of end user applications, test and burn-in, and equipment and processes to give the full technology perspective to symposium attendees."
To register for or learn more about the symposium, contact Bette Cooper at (650) 988-7125 or bcooper@meptec.org, or visit MEPTEC at www.meptec.org.