EIPC Reliability Workshop, Tamworth, UK, September 22, 2016

Estimated reading time: 17 minutes

Birch reviewed the principles of IST: After pre-conditioning to simulate assembly and rework, the coupon was thermally cycled electrically, through a separate heating circuit independent of the vias, and the resistance of the vias was continuously monitored until a change of 10% was observed, at which point the stressing was discontinued before any collateral damage was caused. The exact via whose resistance had increased could be isolated by thermal imaging and further investigated by microsectioning to determine actual failure modes and root causes. All samples were subjected to the same three-minute heating cycle and a nominal two-minute cooling cycle, although cooling was related to mass and heavier constructions were slower to cool. He discussed the critical importance of ensuring that the test coupon design meaningfully represented the design rules and construction of the PCB to be evaluated, and described how standardised coupons and test criteria were being developed to represent the end-use environments and product life cycle expectations of industry sectors such as consumer, computer, telecom, medical, automotive, avionic and aerospace, and satisfy the increasing demand for demonstrated product reliability.

 “Who is responsible for failures, and where are they created?” was the question that Birch set out to explore with what he termed “The Hierarchy of Failure,” which he illustrated as a broad-based triangle with product design at the base and end-use environment at the peak, and PCB manufacturing and quality, and assembly and rework constituting the intermediate levels. Random PCB defects found during assembly-level testing and early in the end-use environment continued to plague the electronics industry, and existing specifications, test methodologies and quality screening techniques were inadequate to eliminate such defects, most of which were latent and not detected by the PCB fabricator’s electrical test. Assembly and rework were the only times the PCB experienced temperatures above the glass transition of the material, and all PCBs had a “potential life”, exposure to assembly and rework determining how much “residual life” would remain. Birch maintained that in-house screening with innovative testing protocols could dramatically reduce the risk of premature defects and improve the understanding of manufacturing capability. And as new technologies continued to evolve, the factors affecting plated-through-hole reliability could be determined.

The fabricator’s viewpoint, based on five years’ experience of IST testing, was presented by Howard Swarbrick and Donna Gorse from Amphenol Invotec. Lack of understanding on the part of the customer was an ongoing issue, typically where customers saw IST testing as a “fit-all” solution and specified it without really appreciating the significance of the test or the meaning of the results, or argued about liability in the event of an apparent premature failure of an unproven design when the number of test cycles had not been realistically defined.

Amphenol Invotec had originally recognised IST testing as a means of evaluating their complete PCB manufacturing process on a regular basis, particularly as a safeguard against the situation where small changes to individual processes might combine to bring unanticipated results, and as a rapid test to determine the robustness of new materials and processes. However, the recent increase in the demand for IST batch release testing had absorbed a huge amount of their machine capacity, and the capital cost of a new machine had to be weighed against investment in equipment to enhance their capability. Although there was some opportunity for outsourcing the testing, the overall capacity presently available in Europe was limited.

IST acceptance criteria were often imposed on PCB fabricators without due consideration of individual design parameters such as material content, construction and aspect ratio. For example, a complex flex-rigid build with multiple flex layers and high number of no-flow prepregs would have a totally different thermal expansion characteristic than a rigid FR-4 multilayer with the equivalent number of layers, but within some market sectors a pre-determined number of IST cycles (typically 400) had been decreed as the pass-fail standard. Swarbrick cited many similar instances of pass-fail criteria being “inflicted” upon the fabricator by the customer, generally without any known heritage that the design was capable of achieving this expectation.

On a positive note, a prime space OEM had proposed that complex designs be subject to an acceleration study before pass-fail criteria were set. Ideally, such a study would be undertaken before the design was finalised but this was rarely the case and the work was undertaken on live orders with a customer expectation that the IST results would be favourable. And although IST testing was still relatively new in the space sector, there were many examples of product “up there flying” with PCBs manufactured before IST testing was specified, and repeat orders placed on new fabricators were now expected to pass IST despite no heritage of results. At the other extreme, some customers were specifying IST batch release on low layer-count single-stage bonded rigid FR-4 multilayers!

Donna Gorse discussed several actual case histories, with examples where, because of non-representative design parameters, the customer-supplied microvia test coupons failed while the circuits themselves were fully acceptable and job had to be scrapped and re-made with plating process conditions adjusted to ensure that the coupons would pass, regardless of the fact that they were not representative.

She demonstrated that IST could also reveal poor copper-to-copper connection between innerlayer and through-hole, even if no separation was evident on a micro-section after several thermal shocks. The issue with this observation was that IST coupons tended to be designed to check small via holes, whereas this type of defect was more often associated with larger component holes, and the coupon could pass test even if the circuit itself was potentially defective.

PCBs for space applications were still specified with a fused tin-lead finish, and some anomalous results had been observed where microsectioning revealed cracks in the plated-through hole that had been bridged by tin-lead even though the test temperature was significantly below reflow temperature. Some sort of diffusion effect was believed to be the cause, although localised hot-spots had not been ruled out.

There were still some regional market sectors, Israel being an example, that continued to promote HATS as means of checking the robustness of product. Consequently, IST could not yet be considered a universal standard, and there was some concern that the equipment and coupon-design expertise was single-source. Lead-time for coupon design could have a negative effect on quick-turn work, and it was suggested that PWBIS work more closely with CAD and CAM vendors to enable coupon design data to be supplied along with the PCB data, or generated by the fabricator’s front end engineers.

What was the end-user’s perspective? Andy Lewis from Airbus Defence and Space began his presentation by defining reliability as the probability that an item would perform its intended function for a specified time interval under stated conditions. He made it clear that one size did not fit all—different applications required and expected different performance levels in order to achieve an acceptable level of product reliability—and that the level of testing and verification required to demonstrate reliability needed to be commensurate with the end application and with the criticality of the final product. The ability of a design to be realised, and its subsequent reliability, were functions of the design and the regulatory or specification constraints that may have been applied. He added that reliability should be kept in perspective with respect to value, and should not be confused with conformity to a pre-set or agreed range of values: “If it passes 10 seconds solder float, it’s OK…”

Airbus Defence and Space had investigated, and subsequently invested in, IST capability as a consequence of two high-cost PCB incidents, one of which related to design, and one to PCB fabrication. In each instance, standard release testing at the bare board stage had failed to reveal any issues, whereas post-assembly testing revealed issues that could have been detected with extended environmental testing or, in a shorter timescale, with IST. The space industry prohibits the reuse of soldered components, and a number of high-cost, long-lead time components were involved, so it was not just the cost of scrapped components but the potential cost of $800,000 per day for a launch delay that focused their attention.

Although Airbus still recognised that the primary function of IST was as a tool for PCB manufacturers to support process development and improvement, the company had chosen to utilise IST as a screening method for all PCBs above a certain technology level, to prevent long-lead-time components being committed and scrapped due to latent manufacturing or design-related anomalies. A 500-cycle test was selected, with the upper temperature as close to the Tg of the material as the surface finish would allow, and it was considered that a coupon that successfully achieved 500 IST cycles could normally be considered thermally robust and “reliable” for most applications.

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