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Beyond Design: FPGA PCB Design Challenges

Field programmable gate arrays (FPGAs) are now commonplace in the majority of digital designs. These high-speed, high-gate/pin count devices, that once only provided glue logic, are now offering embedded processors, digital signal processors (DSPs), memory blocks and numerous input/output (I/O) pins in one massive ball grid array (BGA) package. Not to mention the considerable number of power supplies that are required to power the device. This added complexity has introduced many PCB layout challenges–apart from the obvious fanout and route of the fine pitch BGA. The reason for this added complexity is that EDA design tools have not kept pace with the growth in FPGAs. Rudimentary PCB layout tools were developed for designing PCBs, containing components with non-programmable pins such as processors and application specific integrated circuits (ASICs), and may not be suitable to FPGA integration. 

The primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup or increase the time required to integrate the FPGA with the PCB. Engineers generally do not consider FPGA pin assignments that expedite the PCB layout. Hundreds of logical signals need to be mapped to the physical pin-out of the device, and they must also harmonize with the routing requirements whilst maintaining the electrical integrity of the design. 

To further frustrate the situation, FPGA I/O assignment is typically in a constant state of flux throughout the design process. Consequently, many PCB designs must be reiterated simply because the board and the FPGA design teams did not have the I/O pin-out synchronized. This has happened to me in the distant past. The board may go through the process of pre-layout simulation, place and route and then a post layout simulation, to verify all the timing is perfect, only to find on testing, the assembly, that the FPGA I/O pin-out is incorrect on the BGA footprint—damn! Meanwhile, days later, I had rerouted, run design rule checks, re-simulated the layout and exported the deliverables. 

Also, from a PCB layout point of view, crossovers of the connections should be minimized to give the router the best possible chance of completion. No matter how good the routing technology, crossovers will generally require two more vias per connection and hence more signal layers to route. One should consider: 

• Reducing the number of vias to minimize signal inductance, thus transmitting and receiving the signal at a higher quality. 
• Keeping the trace length of signals to a minimum to reduce transmission line losses, thereby improving signal quality.

To read this entire article, which appeared in the June 2017 issue of The PCB Design Magazine, click here.