-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueWhat's Your Sweet Spot?
Are you in a niche that’s growing or shrinking? Is it time to reassess and refocus? We spotlight companies thriving by redefining or reinforcing their niche. What are their insights?
Moving Forward With Confidence
In this issue, we focus on sales and quoting, workforce training, new IPC leadership in the U.S. and Canada, the effects of tariffs, CFX standards, and much more—all designed to provide perspective as you move through the cloud bank of today's shifting economic market.
Intelligent Test and Inspection
Are you ready to explore the cutting-edge advancements shaping the electronics manufacturing industry? The May 2025 issue of SMT007 Magazine is packed with insights, innovations, and expert perspectives that you won’t want to miss.
- Articles
- Columns
- Links
- Media kit
||| MENU - smt007 Magazine
Novel Approach to Void Reduction Using Microflux Coated Solder Preforms
July 26, 2018 | By A. Lifton, P. Salerno, J. Sidone and O. Khaselev, Alpha Assembly SolutionsEstimated reading time: 8 minutes

Bottom terminated component packages, such as QFN, are becoming increasingly relevant due to their ability to carry high-power dies in a small form factor. With increasing reliability performance requirements, power management components in packages like QFNs are critical to optimizing thermal and electrical performance. Additionally, low voiding is important for decreasing the current path of the circuit to maximize high-speed and RF performances. The market demand for void reduction under thermal pads of QFN components due to shrinking package sizes and increasing power requirements has generated the need to evaluate key process factors that contribute to voiding to design an optimal solution.
The addition of a micro-fluxed preform in conjunction with a low-voiding solder paste and process know-how is seen to create ideal solder volume with minimal voiding. As IPC 7093 specification acknowledges, one of the key concerns with bottom termination components (BTC) such as QFNs is achieving the solder volume required for a high-reliability solder joint. A multitude of processing factors such as reflow profile, reflow atmosphere, pad finish, and stencil design have been assessed in this study to develop a solution for achieving a high-reliability solder joint with low voiding for QFN packages.
Experimental Procedure
A full factorial DOE was designed based on key factors contributing to voiding under bottom termination components. The use of a solder preform was investigated compared to a solder paste only benchmark sample. The key factors in this DOE were identified and selected by subject matter experts from a leader in semiconductor manufacturing, an OEM of specialized test and measurement equipment for radio communications, and a solder manufacturer.
Figure 1: Image of the PCB test vehicle and some of the components used in this DOE.
A custom single layer 1.6 mm PCB test vehicle was designed specifically for this investigation that encompassed numerous variables that can contribute to voiding in bottom termination components. A single-layer PCB design (Figure 1) was chosen so that other factors (i.e., multilayer board and ground planes) would not influence the key factors being addressed in this study. QFN components of various sizes and pin configurations were among the variables addressed and further defined. In this study, only QFN components were selected (Table 1).
Table 1: Component details.
There were two types of test boards generated: one with an immersion tin (ImmSn) plating, which is widely used in automotive application and another with an immersion silver (ImmAg) plating, which is used in high-reliability and high-power application.
The test board also addressed via design including through hole via, no via, and plugged via configurations under the QFN and LCS components. The through hole via had a 0.3 mm diameter with and 0.5 mm diameter resist on top and bottom. The plugged via maintained the same 0.3 mm diameter hole and depth of 0.4 mm with 0.7 mm diameter resist on top and bottom. Vias were configured in a pattern as indicated in Figure 2.
Figure 2: Via design and configuration on the test vehicle.
The investigation also addressed reflow profile and reflow atmosphere. A low voiding SAC305, type 4 solder paste was used for this study with solidus temperature of 217°C and liquidus temperature 220°C. Thermocouples were strategically placed on the QFN32, and QFN64 component locations on the test vehicle. Proven straight ramp and high soak reflow profiles were evaluated as shown in Figure 3.
Figure 3: Reflow profiles using in this study.
The straight ramp profile increased at a rate of 1°C/s until reaching liquidus temperature of 220°C. The test vehicle was subjected to 65 seconds above liquidus (TAL) with peak temperature on the test vehicle reaching 240°C. The high-soak reflow profile increased temperature at a rate of 1°C/s up to 150°C before slowing to a rate of 0.5°C/s up to 200°C to allow more time for the flux to activate the surfaces.
Table 2: Assemblies' configuration details.
The high-soak profile subjected the test vehicle to 50 seconds above liquidus (220°C) with a peak temperature of 240°C on the test vehicle. Finally, both air and nitrogen reflow atmospheres were evaluated in this investigation to further understand the effect of voiding under bottom termination components.
The focus of the investigation involved the use of the micro-flux coated solder preform to increase solder volume relative to fluxing agent and reduce voiding. The use of a SAC305 microflux coated solder preform in conjunction with paste was benchmarked against a solder paste only test vehicle for each of the configurations summarized in Table 2. Four replicate boards of each iteration were processed to ensure statistically viable data.
Figure 4: Solder paste print configuration. (Examples of window pane solder prints on QFN components used in benchmark samples.)
Close to 2,000 data points were generated combining 54 components on each test vehicle and four replicates of each configuration. The solder paste only benchmark samples were printed in a window pane configuration commonly used in the industry for void reduction and shown in Figure 4.
The design of a solder preforms to allow intimate contact with the thermal pad of the component and increase solder volume played a significant role in the results presented in this investigation. Figure 5 represents an example of the use of solder paste only in window pane format on a QFN where mechanical stack-up issues on the component and reflow characteristics of solder paste make it difficult to achieve good voiding.
Page 1 of 2
Suggested Items
Advancing Aerospace Excellence: Emerald’s Medford Team Earns Space Addendum Certification
06/30/2025 | Emerald TechnologiesWe’re thrilled to announce a major achievement from our Medford, Oregon facility. Andy Abrigo has officially earned her credentials as a Certified IPC Trainer (CIT) under the IPC J-STD-001 Space Addendum, the leading industry standard for space and military-grade electronics manufacturing.
Magnalytix and Foresite to Host Technical Webinar on SIR Testing and Functional Reliability
06/26/2025 | MAGNALYTIXMagnalytix, in collaboration with Foresite Inc., is pleased to announce an upcoming one-hour Webinar Workshop titled “Comparing SIR IPC B-52 to Umpire 41 Functional & SIR Test Method.” This session will be held on July 24, 2025, and is open to professionals in electronics manufacturing, reliability engineering, and process development seeking insights into new testing standards for climatic reliability.
IPC Rebrands as Global Electronics Association: Interview With Dr. John W. Mitchell
06/22/2025 | Marcy LaRont, I-Connect007Today, following a major announcement, IPC is embracing the rapid advancement of technology with a bold decision to change its name to the Global Electronics Association. This name more accurately reflects the full breadth of its work and the modern realities of electronics manufacturing. In this exclusive interview, Global Electronics Association President and CEO Dr. John W. Mitchell shares the story behind the rebrand: Why now, what it means for the industry, and how it aligns with the organization’s mission.
Global Electronics Association Debuts; New Name Elevates IPC’s 70-Year Legacy as Voice of $6 Trillion Electronics Industry
06/25/2025 | Global Electronics AssociationToday begins a new chapter for IPC as it officially becomes the Global Electronics Association, reflecting its role as the voice of the electronics industry. Guided by the vision of “Better electronics for a better world,” the Global Electronics Association (electronics.org) is dedicated to enhancing supply chain resilience and promoting accelerated growth through engagement with more than 3,000 member companies, thousands of partners, and dozens of governments across the globe.
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
06/20/2025 | Andy Shaughnessy, I-Connect007It’s been a busy week in this industry, and we have news and articles from the PCB design, fabrication and assembly communities. Some of this news is out of this world. We may be losing the high ground—the really high ground. Columnist Jesse Vaughan explains how the U.S. seems to be falling behind in space, and how this could affect our ability to defend ourselves in the future. We have an update on the U.S.-China tariff talks, which seem to be moving forward, though sometimes at a snail’s pace.