Cavity Board SMT Assembly Challenges (Part 2)

Estimated reading time: 17 minutes

Figure 29 is a picture of a cross-section of a board from Supplier A showing the two corners (side left and right) of the SiP BGAs that are mounted next to each other. U1, that was in the cavity, is showing the warpage and stretched solder joints. On the other hand, U2, the BGA on the surface outside the cavity, is mounted on the same board, just 6 mm away from U1, which is flat with normal solder joints.

Figure 29: Cross-section U1 corners in the cavity (a) and cross-section U2 corners on board surface (b).

Furthermore, failure analysis points out that each one of the three board suppliers impact the BGA solder joints in a unique way. However, only Supplier A caused SMT failures. The cross-section in Figure 30 of passing boards indicates that the joints’ shapes of the packages that are on the PCB surface—not in the cavity (Figure 30b)—are very similar between the three different board suppliers. They all have a normal joint shape and collapse. The BGA joints inside the cavity (Figure 30a), however, had a unique shape for each PCB supplier. Supplier A showed stretched joints. Supplier B had normal to slightly stretched joints, and Supplier C had normal to slight compress joints.

Figure 30: Comparison of BGA solder joints’ cross-section.

The plot in Figure 31 consists of measurements of the BGA joints’ height in the cavity from the three board suppliers. Comparison of the data indicates that the solder joint height of Supplier A was 38.1% higher than Supplier C.

Figure 31: Solder joint height.

Board Local Warpage

The dynamic warpage characteristic of the boards during the reflow cycle was assessed using Shadow Moiré metrology. The topography map of the warpage value across the cavity was measured. Figure 32 indicates the localized board warpage and shape at the cavity area. The dynamic warpage profiles in the cavity area show notable differences between the boards obtained from different suppliers. Supplier A had the highest warpage with a convex shape at room and reflow temperature, explaining the defects seen during assembly. Board Supplier B was fairly flat during room and reflow temperature, and board Supplier C had concave shapes, which shows some compressed joints at the corner, but no failures occurred.

Figure 32: Warpage shape and magnitude for boards from three different suppliers.

Package Z-Height

The package Z-height is a critical parameter for the product. The total package Z-height is defined as the height between the tallest points on the package to the top surface of the board. Figure 33 shows the total Z-height of the two packages: the one on the board surface and the one in the cavity after assembly. In both cases, the height is measured from the board surface to the top of the silicon die.

Figure 33: Package Z-height.

The total Z-height was measured by optical coordinate measurement microscopy (OCMM). Measurement data points were taken from three points on each die as a reference to a nearby point on the top surface of the board. Figure 34 illustrates the measurement points on the triple die package.

Figure 34: Package Z-height.

The Z-height data comparison between U1, the package in the cavity, to U2, the package on the board surface, is shown in Figure 35. The Z-height of U1 is trending down as a function of the board supplier, following the solder joint height in the cavity.

In summary, the mean Z-height of all packages on the PCB surface (outside the cavity) were higher than those in the cavity. Board Supplier C had the largest mean Z-height reduction of 15%, while boards from Supplier B had 8.5%. Board Supplier A had the least reduction in mean Z-height of 4 %.

Supplier A also had the greatest Z-height variation (Figure 35). In fact, because of the large variation of height on Supplier A’s PCBs, the assembled height of some components in the cavity was the same as the component on the surface.

Figure 35: Package Z-height.

Conclusion

This article describes the details of a study of assembling SiP BGA packages into a cavity. It points out the challenges involved in the board cavity design and assembly of components in a cavity. The authors discussed the board design challenge of having a cavity and defining the proper depth of the cavity to accommodate the board fabricator, the product design, and the SMT assembly.

This article also reviewed 3D stencil technologies to allow solder print on two levels. Further, it analyzed the pros and cons of each technology and compared their performance. There is no one selected technology which will fit all needs. The 3D stencil needs to be well designed and selected for the unique application and use.

Acknowledgments

The authors would like to thank Intel’s CPTD Operations and Planning and their colleagues Raiyo Aspandiar and Pubudu Goonetilleke for contributions to this work.

References

2. C. Läntzsch, G. Kleeman, “Challenges for Step Stencils With Design Guidelines for Solder Paste Printing,” Proceedings of the IPC APEX EXPO Conference, 2012.

3. M. Scalzo, “Addressing the Challenge of Head-In-Pillow Defect in Electronic Assembly,” Proceedings of the IPC APEX EXPO Conference, 2012.

4. R. Pandher, R. Raut, M. Liberatore, N. Jodhan, K. Tellefsen, “A Procedure to Determine Head-in-Pillow Defect and Analysis of Contributing Factors,” Proceedings of SMTA International Conference, 2011.

5. D. Amir, R. Aspandiar, S. Buttars, W. W. Chin, P. Gill. “Head-and-Pillow SMT Failure Modes,” Proceedings of SMTA International Conference, 2009.

Dudi Amir is a software engineer and Brett Grossman is a senior staff engineer with Intel Corporation.

This article was originally published in the proceedings of SMTA International 2018.

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