-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current Issue
Spotlight on North America
A North America spotlight exploring tariffs, reshoring, AI demand, and supply chain challenges. Plus, insights on cybersecurity, workforce development, and the evolving role of U.S. electronics manufacturing.
Wire Harness Solutions
Explore what’s shaping wire harness manufacturing, and how new solutions are helping companies streamline operations and better support EMS providers. Take a closer look at what’s driving the shift.
Spotlight on Europe
As Europe’s defense priorities grow and supply chains are reassessed, industry and policymakers are pushing to rebuild regional capability. This issue explores how Europe is reshaping its electronics ecosystem for a more resilient future.
- Articles
- Columns
- Links
- Media kit
||| MENU - smt007 Magazine
Cavity Board SMT Assembly Challenges (Part 2)
July 3, 2019 | Dudi Amir and Brett Grossman, Intel CorporationEstimated reading time: 12 minutes
Figure 24: Cavity KOZ.
This formula is based on experiments with 200-μm cavity depth and can be used as a good starting point for cavity design. It may need additional experiments and adjustments for deeper cavities. For the KOZ outside the cavity (Co), as mentioned in the experiment results, the smearing was the only issue. To minimize the smearing, a KOZ of 0.5 mm and an additional 0.5 mm for HVM variation would be recommended. Note that if a welded technology is used for the stencil, a welding KOZ is also necessary, which will add 1.5mm.
Squeegee Experiment
The impact of the squeegee slit length (Figure 15), blade thickness, and the use of a soft polyurethane squeegee were evaluated. Nine boards—three from each PCB supplier—were printed with paste. The paste volume was measured in the SPI machine. Electroformed Stencil 2 was used with this study. Five different squeegee types were evaluated. Table 5 lists the experiment’s legs.
Table 5: Print study.
The chart in Figure 25 provides the experiment results of the different squeegees. Leg 1 with a 10-mm slit and a 0.2-mm blade showed the best print volume CV.
Figure 25: Squeegee-type print CV study.
Using a polyurethane squeegee with no slit (Leg 5) showed high solder print CV for the BGA outside of the cavity as well as the one inside the cavity. The chart in Figure 26 consists of the different squeegee blade legs and solder volume measured at U1 inside the cavity and U2 on the surface outside the cavity. The solder paste volume at Leg 5—the polyurethane squeegee—had some low paste points and had difficulty in printing the two levels at the same time without causing solder scooping and insufficient solder volume.
Figure 26: Squeegee-type print CV study.
Component Assembly in the Cavity
The assembly yield of a BGA SiP into a cavity was compared to a control BGA SiP outside the cavity, which was placed just 6 mm away from each other (Figure 27). BGA U1 was placed in the cavity while BGA U2 was outside of the cavity.
Figure 27: Assembled board.
The data was collected from multiple builds with Stencil 2 using a 0.2-mm slit squeegee blade and a 10-mm slit. After assembly, the boards were examined by X-ray for opens and shorts. Selected units went through failure analysis for cross-sections. To add HVM variability multiple board supplier were used. The results are summarized in Table 6.
Table 6: SMT assembly yield.
Failure Analysis
There were two surprises: the first one was that all defects came from one PCB supplier regardless of build time and shift although the same process was used at SMT to mount all boards. The second surprise was that the defects were open due to head-on-pillow (HoP) with a signature indicating excessive warpage. The SiP BGA that was selected had a stiffener to control its warpage during reflow to a minimum. The initial risk for the defect was presumed to be bridging due to the excessive paste and large paste volume variation at the edges and corner of the cavity lands. Figure 28 shows stretched joints at the package corners with classic HoP defects, which has been shown in many industry papers [3] as an indication of high warpage of the package. However, this was not the case in this experiment.
Figure 28: BGA head-on-pillow defect.
This defect, shown in Figure 28, is a result of localized warpage of the board in the cavity area, and not the BGA package. It was known that local warpage is a contributor to open HiP defects in SMT [4 & 5],but it has not previously been shown as being the only cause for this defect.
Page 3 of 4
Testimonial
"The I-Connect007 team is outstanding—kind, responsive, and a true marketing partner. Their design team created fresh, eye-catching ads, and their editorial support polished our content to let our brand shine. Thank you all! "
Sweeney Ng - CEE PCBSuggested Items
AQUANOX A4727 and A4625 Lead KYZEN Offerings at SMTA Oregon Expo and Tech Forum
05/06/2026 | KYZENKYZEN, the global leader in innovative environmentally responsible cleaning chemistries, will exhibit at the SMTA Oregon Expo and Tech Forum scheduled to take place Thursday, May 19 at the Wingspan Event and Conference Center in Hillsboro, Oregon.
Connect the Dots: Designing for the Future of Manufacturing Reality—Surface Finish
05/07/2026 | Matt Stevenson -- Column: Connect the DotsWhen designing the complex boards that many electronic devices require to operate, designers should consider manufacturability at every step. This is my last article focused on designing for the always-evolving manufacturing reality. Choosing the right surface finish has always been important. If you are creating intricate designs with a wide variety of components, like for an ultra-high density interconnect (UHDI) board, surface finish is a critical last step.
Indium to Showcase High-Performance AI Application Solutions at SEMICON SEA 2026
05/01/2026 | Indium CorporationAs a leading provider of advanced materials solutions for today’s demanding AI applications, Indium Corporation® will feature its high-reliability product portfolio at SEMICON SEA 2026, May 5-7, in Kuala Lumpur, Malaysia.
ACCM Unveils Negative and Near-zero CTE Materials for Large-Format AI Chips
04/21/2026 | Advanced Chip and Circuit MaterialsAdvanced Chip and Circuit Materials, Inc. (ACCM) has launched two new materials: Celeritas HM50, with a negative coefficient of thermal expansion (CTE) of -8 ppm/°C to offset the positive CTE and expansion of copper with temperature on circuit boards, and Celeritas HM001, with near-zero CTE and the low-loss performance needed for high-speed signal layers to 224 Gb/s and faster in artificial intelligence (AI) circuits.
SMTA Ultra HDI Symposium, Day 2: Fragile Supply Chains, Fierce Innovation
04/14/2026 | Marcy LaRont, I-Connect007The Arizona weather yielded another beautiful day as we gathered for the second day of SMTA’s annual UHDI symposium. After the first full day discussing the role of AI in business and the how-tos of implementation, Avondale Mayor Mike Pineda kicked off day two, proud to showcase his city and to declare its important place in the continued development of the West Valley, an increasingly important area for tech and manufacturing.