Decoupling Capacitors’ Impact on Power and Signal Integrity

Estimated reading time: 1 minute

This article will discuss the effect of decoupling capacitors upon a PCB’s power and signal integrity. The study was performed with post-layout co-simulation of power and signal integrity to analyze power distribution network impedance, simultaneous switching noise, and eye diagrams.

Introduction

It is crucial for hardware designers to identify the resonant frequency of each element (e.g., bypass/decoupling capacitor, planar capacitance, and interconnect inductance) of the power distribution network (PDN) on a PCB and its impact on power integrity. A PCB with poor power integrity—such as a higher-than-targeted PDN impedance across the wideband range—results in simultaneous switching noise (SSN) and a shrunken eye diagram of the signal transmitted by the IC that draws power from the PDN. This article demonstrates the post-layout co-simulation of power and signal integrity using Mentor HyperLynx to analyze the impact of decoupling capacitors upon PDN impedance, SSN, and eye diagrams.

Analysis and Results

A PCB containing a system-on-a-chip (SoC) with DDR4 memory interface is laid out. In Figure 1a, the PDN named 1.2V on layer 4 supplies power to a memory interface that consists of one memory IC highlighted in blue. Meanwhile, the ground or reference plane, highlighted in green, is laid out on layer 5. The memory IC has 13 BGA power pins. The footprint of the 0.22-uF decoupling capacitor (highlighted in brown) in a 0201 package dimension is placed across each of the power pins and the ground. Additionally, the footprint of bypass capacitors, 10 uF and a 1 uF respectively (highlighted in brown as well), is placed across the 1.2V power net and ground. The eight data signals of this memory interface are shown in Figure 1b.

To view the rest of this article, which appeared in the August 2019 issue of Design007 Magazine, click here.