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Practical Verification of Void Reduction Method for BTC Using Exposed Via-in-pad
December 16, 2019 | Alfredo Garcia, et al, Sanmina and NokiaEstimated reading time: 1 minute
Abstract
Void reduction strategies used with different levels of success throughout the industry include managing reflow profile parameters, solder paste deposit volume and solder paste type, stencil aperture cut to different geometries, thermal pad geometries with and without solder mask webs, vacuum-assisted reflow, sweep stimulation of PCB substrate, use of solder preforms, tinning of the components pads before placement and reflow, I/O aperture design to overprint at the toe of the pad, and exposed via-in-pad [1–8]. The translation of these methods and their combinations for void control on the thermal pad of bottom-terminated components (BTCs) has been met with different levels of success in volume production.
The method explored in this article regards the use of exposed via-in-pad. A dedicated test vehicle was designed for two types of QFN components. The main variables accounted for were the component size, number of exposed vias in the thermal pad, via pitch, via size, and solder paste coverage. The responses sought in this experiment include a thermal pad void level and solder wicking down the via barrel with resulting solder protrusion on the opposite side of the PCB.
The results indicated that solder will wick down the exposed via-in-pad regardless of the via diameter and solder paste coverage. Despite this finding, there were no defects recorded like component tilting, skewing, opens, or solder bridging. Specific configurations attained voiding levels in the thermal pad below 25%; however, other configurations did show a void level for the thermal pad up to 50%. A discussion will be presented regarding the effect of the board thickness and the geometry of the via array on the thermal pad solder coverage and voiding level.
To read this entire article, which appeared in the November 2019 issue of SMT007 Magazine, click here.
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