-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueAll About That Route
Most designers favor manual routing, but today's interactive autorouters may be changing designers' minds by allowing users more direct control. In this issue, our expert contributors discuss a variety of manual and autorouting strategies.
Creating the Ideal Data Package
Why is it so difficult to create the ideal data package? Many of these simple errors can be alleviated by paying attention to detail—and knowing what issues to look out for. So, this month, our experts weigh in on the best practices for creating the ideal design data package for your design.
Designing Through the Noise
Our experts discuss the constantly evolving world of RF design, including the many tradeoffs, material considerations, and design tips and techniques that designers and design engineers need to know to succeed in this high-frequency realm.
- Articles
- Columns
- Links
- Media kit
||| MENU - design007 Magazine
Cadence Expands Design IP Portfolio with 56G Long-Reach PAM4 SerDes
May 18, 2020 | Business WireEstimated reading time: 2 minutes

Cadence Design Systems, Inc. recently announced the availability of 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies.
Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. To address this broader market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimized power, performance and area (PPA). For more information on the 56G long-reach PAM4 SerDes, please visit www.cadence.com/go/56GSerDes.
Cadence is ready to engage with customers immediately on 5G, compute server processor and machine learning workload-accelerator system-on-chip (SoC) design enablement. The Cadence® 56G long-reach SerDes IP delivers design excellence in support of the Cadence Intelligent System Design™ strategy, offering designers a number of benefits, including:
- Best-in-class 36db+ insertion loss using Cadence’s well-proven multi-rate DSP technology
- Industrial temperature range, CPRI data rate support and per-lane PLL are ideal for 5G applications
- 56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process
- Fully compliant with the IEEE standard specification
- Programmable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
- Optimal data recovery through the programmable DSP-based architecture, which allows optimal power delivery for a given reach and provides superior data recovery under lossy and noisy channel conditions
- Improved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design
“We are pleased to see Cadence expand its PAM4 offerings to include 56G and extend support to TSMC N7 and N6 process technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading edge SerDes IP and TSMC’s advanced process technologies will help our customers unleash their silicon innovations for emerging 5G and hyperscale data center applications.”
“After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our offering to include PPA-optimized 56G-LR to address the connectivity needs of the 5G infrastructure and AI/ML market. This new PAM4-based 56G-LR SerDes is based on Cadence’s well-proven multi-rate DSP technology,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “The availability of Cadence’s 56G long-reach SerDes IP on the TSMC N7 and N6 processes accelerates the adoption and deployment of cost-effective 100G and 400G networks.”
Suggested Items
DownStream Acquisition Fits Siemens’ ‘Left-Shift’ Model
06/26/2025 | Andy Shaughnessy, I-Connect007I recently spoke to DownStream Technologies founder Joe Clark about the company’s acquisition by Siemens. We were later joined by A.J. Incorvaia, Siemens’ senior VP of electronic board systems. Joe discussed how he, Rick Almeida, and Ken Tepper launched the company in the months after 9/11 and how the acquisition came about. A.J. provides some background on the acquisition and explains why the companies’ tools are complementary.
Elementary Mr. Watson: Retro Routers vs. Modern Boards—The Silent Struggle on Your Screen
06/26/2025 | John Watson -- Column: Elementary, Mr. WatsonThere's a story about a young woman preparing a holiday ham. Before putting it in the pan, she cuts off the ends. When asked why, she shrugs and says, "That's how my mom always did it." She asks her mother, who gives the same answer. Eventually, the question reaches Grandma, who laughs and says, "Oh, I only cut the ends off because my pan was too small." This story is a powerful analogy for how many PCB designers approach routing today.
Connect the Dots: The Future of PCB Design and Manufacturing
07/02/2025 | Matt Stevenson -- Column: Connect the DotsFor some time, I have been discussing the increasing complexity of PCBs and how designers can address the constantly evolving design requirements associated with them. My book, "The Printed Circuit Designer’s Guide to… Designing for Reality," details best practices for creating manufacturable boards in a modern production environment.
Siemens Turbocharges Semiconductor and PCB Design Portfolio with Generative and Agentic AI
06/24/2025 | SiemensAt the 2025 Design Automation Conference, Siemens Digital Industries Software today unveiled its AI-enhanced toolset for the EDA design flow.
Cadence AI Autorouter May Transform the Landscape
06/19/2025 | Andy Shaughnessy, Design007 MagazinePatrick Davis, product management director with Cadence Design Systems, discusses advancements in autorouting technology, including AI. He emphasizes a holistic approach that enhances placement and power distribution before routing. He points out that younger engineers seem more likely to embrace autorouting, while the veteran designers are still wary of giving up too much control. Will AI help autorouters finally gain industry-wide acceptance?