Real Time with… SMTAI 2020: Technical Conference Review

Estimated reading time: 16 minutes

Ejiri works in R&D, downsizing and reducing the weight of electronic components by using the molded interconnect device (MID) process. The MID process has become increasingly important over the past few years. MID has been introduced as an important and accurate method of developing 3D electronic parts.

This work is concerned with Cu paste for MID, and he explained the development status of Cu paste, along with its low-temperature curing. To allow the use of thermoplastic as the base materials—that is PET, polycarbonate, polypropylene, and liquid crystal polymers—Ejiri developed a low-temperature solder paste and a coating material to increase adhesion. To increase the density of the Cu paste using printing, he explained their use of aerosol jet printing that allows geometries smaller than 140 microns while maintaining thickness to permit a lower resistance of the traces.

Figure 5: New process.

Figure 6: Cu wiring on 3D material (LCP).

Farris presented an engaging talk on the emerging and exciting trend in the automotive industry: the adoption of advanced LED headlamp lighting systems. These systems drive challenging placement requirements for LED packages. In this presentation, he showed a review of these unique challenges and discussed a novel approach to high-accuracy placement of LED packages enabling a scalable production solution: the proprietary top-side assembly placement (TAP) process.

Some of the challenges include:

• Automotive LED headlamps require precise alignment of LED emitting feature(s)
• Requires precise placement to assembly features (tooling holes) and to other LEDs under SMT process conditions
• LED position within its packaging does not meet assembly performance criteria X,Y, and Theta
• Standard SMT assembly is based on lead to pad, not a device top-side feature

After the TAP process is presented in detail (and how it addresses these challenges), then he presented a case study where they implemented TAP for a high-accuracy LED headlamp applications, including a thorough analysis of the results before and after each step.

Figure 7: Introduction to TAP.

The challenge with this type of assembly is that the LED must be precisely aligned with its lens, but the device is aligned to the package leads. The TAP process corrects this type of challenge.

Optical parts placement objectives include:

• Achieve LED placement accuracy within ±25 micron accuracy post-reflow
• Use of two drill holes on each circuit for alignment reference
• Placement accuracy measured from a reference hole on each circuit
• Pick-and-place of typical SMT devices for LEDs to mimic the process
• Baseline accuracy
• LED placement accuracy on a glass plate
• LED placement accuracy verification on panel
• Dry assembly no-wet process
• Adhesive and solder paste pre- and post-reflow
• Solder paste printing and inspection
• Low-temperature cure adhesive dispensing
• AOI for solder print characterization
• Pick-and-place
• Reflow profile setup
• X-ray for void inspection
• AOI accuracy measurement
• Cross-section test

The case study showed the alignment reliability, as well as measurements of the soldering quality.

Figure 8: The TAP process flow utilizing an Inspection station to measure device to package.

This article was the second part of a series of studies on the new generation of electronic contact challenges and component interconnects technology for high-end computer products. These products include computer server and data storage for cloud computing applications at the data center, as well as core routers for service providers, edge and branch routers for enterprise networking companies, and small switch and wireless router for commercial and small and home office. All these cloud computing products require high data speed in terabytes per second and high signal integrity for the massive mobile users and IoT application whenever and wherever they wish to connect.

To achieve such mobility and signal integrity, the major focus is to see electrical interconnections between the CPU/GPU and component and contact interconnect between PSU and MB header in the system. Due to the large number of edge-card connections such as DIMM, PCIe, etc. are designed into modern computer systems, in part one of the study, a new generation of dual-contact interconnect methodology, component level contact configuration, and interconnect reliability were assessed.

Figure 9: Dual-contact interconnection and the importance of a new plating process.Page 2 of 7

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