-
-
News
News Highlights
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLearning to Speak ‘Fab’
Our expert contributors clear up many of the miscommunication problems between PCB designers and their fab and assembly stakeholders. As you will see, a little extra planning early in the design cycle can go a long way toward maintaining open lines of communication with the fab and assembly folks.
Training New Designers
Where will we find the next generation of PCB designers and design engineers? Once we locate them, how will we train and educate them? What will PCB designers of the future need to master to deal with tomorrow’s technology?
The Designer of the Future
Our expert contributors peer into their crystal balls and offer their thoughts on the designers and design engineers of tomorrow, and what their jobs will look like.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - design007 Magazine
New Siemens Aprisa IC Place-and-Route Software Version Targets Faster Performance Improvements
October 13, 2021 | SiemensEstimated reading time: 1 minute

Siemens Digital Industries Software announced that the latest release of its Aprisa™ physical design solution is now available. Aprisa 21.R1 has achieved major performance and technology advancements, including dramatic improvements in both runtime and memory footprint reductions. For customers, these enhancements can translate to lower design costs and faster time-to-market.
The technology advancements available in Aprisa 21.R1 demonstrate Siemens’ commitment to delivering best-in-class physical design Integrated Circuit (IC) solutions to its Electronic Design Automation (EDA) customers. Since completing the acquisition of the Aprisa portfolio in December 2020, Siemens has more than doubled the Aprisa R&D team as part of a substantial investment in the Aprisa technology portfolio.
The latest release of Aprisa targets advanced technology nodes and includes the following milestones and highlights:
- Average full-flow runtime reduction of 30 percent compared to the previous release, and up to 2X faster runtimes for larger, more challenging designs.
- Enhancements to all major place-and-route engines, from placement optimization to clock tree synthesis (CTS) optimization, route optimization and timing analysis. The benefits of these performance enhancements can be observed on almost all IC designs, and especially on large designs with complicated multi-corner multi-mode (MCMM) features. On these challenging designs, Aprisa has proven to run up to 2X faster than the previous generation.
- Up to 60 percent memory footprint reduction; Aprisa has reduced, on average, 30 percent full-flow peak memory usage for large designs, and up to 60 percent for complex designs, compared to the previous generation. This greater efficiency enables even larger designs with complicated MCMM to be completed on servers with less available RAM.
- 6nm/5nm/4nm design enablement. Siemens has collaborated closely with leading foundries to enable Aprisa for advanced nodes. Aprisa is fully certified for 6nm processes, and Siemens has implemented all required design rules and features for the design enablement of 5nm and 4nm nodes. Final certifications, in collaboration with the world’s leading foundry partners, are in progress.
- Extended support for multi-power domain (MPD). The extended functionalities greatly increase the flexibility and completeness of MPD support, which is critical for extreme low-power designs.
“This new release reconfirms Siemens’ commitment to providing truly world class physical design technology to our EDA customers,” said Inki Hong, division director of the Aprisa product line for Siemens Digital Industries Software. “With Aprisa 21.R1, our customers can work more efficiently with larger and more challenging designs than ever before.”
Suggested Items
Würth Elektronik Now an Infineon ‘Preferred Partner’
03/13/2025 | Wurth Elektronik eiSosWürth Elektronik, one of the leading manufacturers of electronic and electromechanical components, is broadening its collaboration with semiconductor manufacturers.
Elementary Mr. Watson: Ensuring a Smooth Handoff From PCB Design to Fabrication
03/13/2025 | John Watson -- Column: Elementary, Mr. WatsonAt the 2020 Tokyo Summer Olympics, the U.S. men's 4x100-meter relay team had high hopes of winning a medal. The team comprised some of the fastest sprinters in the world, but something went wrong. In a relay, four runners must smoothly pass their baton to the next runner inside a zone on the track. If a runner drops the baton or it’s passed outside the zone, the team risks disqualification. The U.S. team’s pass between the second and third runner was messy, slowing them down. By the time the last runner received the baton, the team had lost too much time. They finished sixth in their heat and didn’t qualify for the final.
Ventec International Group Announce Launch of VT-47LT IPC4101 /126 Prepreg for HDI
03/12/2025 | Ventec International GroupVentec International Group announce launch of VT-47LT IPC4101 / 126 Prepreg. Are Microvia Failures Plaguing Your HDI Any Layer Designs? High-density interconnect (HDI) designs are pushing the envelope - higher layer count HDI relies on complex microvia designs: skip vias, staggered microvias, and stacked microvias in sequential laminations.
TI Introduces the World's Smallest MCU, Enabling Innovation in the Tiniest of Applications
03/12/2025 | PRNewswireTexas Instruments (TI) introduced the world's smallest MCU, expanding its comprehensive Arm® Cortex®-M0+ MSPM0 MCU portfolio. Measuring only 1.38mm2, about the size of a black pepper flake, the wafer chip-scale package (WCSP) for the MSPM0C1104 MCU enables designers to optimize board space in applications such as medical wearables and personal electronics, without compromising performance.
Speaking the Same Language as Your Fabricator
03/12/2025 | Andy Shaughnessy, Design007 MagazineWe do indeed have a failure to communicate; designers and fabricators often seem to be talking past each other, which can lead to jobs being put on hold. We asked Jen Kolar, VP of engineering for Monsoon Solutions, and columnist Kelly Dack to share their thoughts on ways that we can break down the communication barrier between design and fabrication. As they point out, a design kickoff checklist and a solid review process can be invaluable tools in a designer’s toolbox.