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Optimizing Test Engineering Practices for High-Mix Electronics Manufacturing
August 15, 2022 | Mark Laing, Siemens Digital Industries SoftwareEstimated reading time: 11 minutes
Guideline #3: Automate Test Plan Generation
A test plan contains a set of rules that are used to determine the accessibility of locations on the board. It defines the settings or constraints used by the analysis engine to determine which features on each net are accessible to be probed, and which are not. Once these individual features are reviewed across each net, the results can be used to determine if that net can be probed or not.
The results of probe analysis usually indicate that each individual feature is: not accessible, accessible without a test probe, or accessible with a test probe. The constraints of a test plan allow the software to determine which of these three categories each feature falls into.
Figure 3.1: Probe analysis results.
Although a number of these constraints are used by both ICT and flying probe, some are specific to each technology. Probe sizes are specific to ICT and it is important that the different probe sizes of 100 mil, 75 mil and 50 mil are sized correctly and don’t conflict with each other. ICT probes almost always hit the center of the feature, but for flying probe machines, probes can be offset from that location. This is usually what happens when surface mount component pins are probed. The touch point of the flying probe will be offset away from the body of the component and will hit the end of the pad so it will not be deflected by the pin or solder fillet and will not create a false connection through the joint due to probe pressure.
Each unique group of analysis settings can be considered a complete test plan. Many test plans have a group of core routines, such as ICT bottom, ICT both, flying probe top, flying probe both. There may be conservative and aggressive versions of each plan as well. For example, a conservative plan would use 25 mil as a minimum target diameter for ICT and 100-mil and 75-mil probes. An aggressive test plan may use 20-mil targets on the bottom side and introduce a 50-mil probe size.
Pre-conditions can be used to further control how automated algorithms prioritize and then place probes during the test plan stage. There may be cases in which specific components need to be avoided even if they are accessible, or where probes should be placed, even if alternatives exist.
It may also be necessary to power up a board for certain types of testing, therefore, power injection probes need to be assigned to specific nets to achieve this.
There may be more complex scenarios requiring multiple probes, in which some are placed and some are not. Being able to review each point on a net and understand why it was not possible to place a probe on that feature can save a lot of time. Valor Process Preparation, for example, provides a graphical view of the board, highlighting the net. Below the graphical view, accessibility results are presented dynamically, enabling the list to be filtered further down to a single feature if needed.
Figure 3.2: Dynamically reviewing probe results with layout and schematic information.
The goal of any test engineering solution is to place all required probes automatically. However, there are cases following the probe review in which adjustments need to be made. A graphical drag-and-drop function can be used to move a probe from one position to another. The software should be able to constrain the probe to only that area or feature that is valid.
Probes are not the only adjustment that may be necessary. The probe labels may need to be moved away from other probe labels and graphics so that they are clearly readable. This capability can be particularly useful for ICT purposes when a clear probe label map is needed inside the fixture.
Guideline #4: Facilitate Reporting and Data Transfer Reporting
Reports are a crucial aspect of test engineering, in which usable results are delivered in a timely fashion to a variety of users. The output format should be flexible, supporting HTML for readability, CSV files for importation into Excel, as well as formats for data transfer to other systems.
Graphical representations should also be supported. For example, probe placement results should show nets with unplaced probes.
Figure 4.1: Example of an HTML testability report.
Data Export: Ultimately, the data produced by the test engineering solution needs to be passed to the machine software. The final test program will be created from this data. Each test machine has its own specification on how to convey layout, BOM, test attributes, test probes, accessibility, and panel information to the target machine. Some test systems use a single file, some use multiple files.
The more complete the test engineering data, the less work that needs to be done on the target machine. This is why it is important to use these test engineering applications to the fullest as they are the only ones that have the full data set available to them. Be aware that many legacy formats are still in use: Some of them predate surface mount technology and will filter the full data set provided by the test engineering application.
Probe Import: There are multiplexed and non-multiplexed test systems on the market. Multiplexed test systems switch their resources through relays, so it is not possible to switch every net to every resource and therefore, specific channels must be assigned to the board during program creation. Non-multiplexed test systems can switch all resources to any net and therefore can use the initial assignment of test channels as presented.
In the case of multiplexed systems, the programming software should support importation of the final probe channel map after the program has been created in order to ensure that the fixture and debug material align with the program. Files created by the test program generation software tell the test engineering software what the final channel names are, replacing the existing ones.
Learn more about Valor Process Preparation, or try Valor Process Preparation for free with our 30-day free trial.
Mark Laing is a business development manager for Siemens Digital Industries Software.
Additional content from Siemens Digital Industries Software:
- The Printed Circuit Designer’s Guide to... Stackups: The Design within the Design by Bill Hargin
- The Printed Circuit Assembler's Guide to... Smart Data: Using Data to Improve Manufacturing?by Sagi Reuven and Zac Elliott
- The Printed Circuit Assembler's Guide to… Advanced Manufacturing in the Digital Age?by Oren Manor?
- The Printed Circuit Designer’s Guide to… Power Integrity by Example by Fadi Deek
- Siemens’ 12-part, on-demand webinar series?“Implementing Digital Twin Best Practices?From?Design Through Manufacturing”
- Rountable: RealTime?with...?Siemens and Computrol: Achieving Operational Excellence in Electronics Manufacturing??
- You can also view other titles in our full I-007eBooks library.
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