Reduce Board Skyline With Solid Cavity Design

Estimated reading time: 2 minutes

With the increasing shrinkage of modern electronics in both board size and product volume, it’s becoming more difficult to mount components to the PCB surface and still meet volumetric requirements. To avoid chip-on-board (COB) processing, board cavities can help mitigate the Z-axis skyline volumetric issues and allow for components that would otherwise not fit within the skyline to be used.

 As the name implies, a cavity is the removal of some of the board material to expose traces and contact pads on inner layers of the PCB. This is done to allow attachment of the component to these exposed pads rather than pads on the surface of the PCB (Figure 1). To form cavities, several special processes need to be considered. Among these are inner layer plating, particularly the effects of plating and surface finish on inner layer impedance for signal integrity; sequential lamination; surface finish on exposed inner layer pads; and the use of controlled depth milling to form the cavity, just to name a few.

Figure 1: A typical cavity as it appears in an ECAD software tool.

One of the first items of concern is the effect of plating and surface finish on impedance of the inner layers. When cavities are formed without sequential lamination, the plating and surface finish needed to support the soldering process will add conductive material thickness to the exposed areas of the inner layer. This in turn will cause an impedance discontinuity due to these different thicknesses of the traces.

Additionally, the removal of the reference planes from one side of the conductor changes the structure of the transmission line from a stripline on inner layer to a microstrip in the cavity. Most ECAD and SI tools do not support different transmission line structures on the same layer of the board. There are some solutions to this conundrum: Rather than relying on the built-in transmission line structures of ECAD tools, the designer can manually calculate the controlled impedance trace widths for the stripline and microstrip sections and then use area constraint rules to define the widths both in the cavity and on the remainder of the layer.

One possible way around this issue is to use sequential lamination to allow plating on the entire layer. But sequential lamination poses its own problems. First, it is a more costly and time-consuming process. Second, it adds fabrication allowances. It may also require the use of blind and/or buried vias to make the connections between layers. The multiple plating cycles needed for sequential lamination can cause other fabrication issues. It is recommended that the fabricator be consulted on any sequential lamination PCB design.

To read this entire article, which appeared in the July 2023 issue of Design007 Magazine, click here.