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Cadence Collaborates with Broadcom to Implement AI-Driven Solutions
October 19, 2023 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced a collaboration with Broadcom Inc. to implement new AI-driven design flows to accelerate the delivery of their innovative 3nm and 5nm designs. Using the AI-driven Cadence® Cerebrus™ Intelligent Chip Explorer, many business units achieved impressive performance, power and area (PPA) benefits. Given the complexity and size of Broadcom’s product designs at advanced nodes, AI-driven technology can be a game changer to achieve aggressive time to tapeout schedules.
Due to the advanced capabilities of Cadence Cerebrus, Broadcom has been able to automate tasks through AI, for improving final design data and turnaround time. For example, the floorplan exploration capability helps automatically determine the optimal chip design floorplan, saving PPA. The AI model reuse capability enables Broadcom to apply previous design learnings to their next-generation designs, reducing the time to optimized results. Finally, the easy-to-use interface provides interactive analytics, offering valuable insights into design data and easy debug.
“We use a wide portfolio of Cadence solutions across our business units, and we have seen outstanding PPA improvements from the use of the AI capabilities of Cadence Cerebrus,” said Yuan Xing Lee, Vice President and Head of Central Engineering, Broadcom. “Over the last year, we have seen accelerated adoption of Cadence Cerebrus AI technology across multiple business units within Broadcom and we look forward to taking advantage of this technology in our next generation of products. Cadence has been a key silicon design partner for many years now, and we look forward to continuing to work together to achieve our design goals and deliver high-quality designs to customers.”
“With the AI-driven capabilities of Cadence Cerebrus, Broadcom successfully reduced manual tasks so they could focus on higher-impact, strategic work while meeting PPA goals,” said Dr. Chin-Chi Teng, Senior Vice President and General Manager, Digital & Signoff Group, Cadence. “Today’s designs are very complex, and through our continued collaboration, we are working together to ensure that Broadcom is able to utilize our AI capabilities to deliver compelling designs to market faster.”
The Cadence Cerebrus Intelligent Chip Explorer is part of the broader digital full flow, which provides optimal PPA and reduced turnaround time. It supports Cadence’s Intelligent System Design™ strategy, providing system-on-chip (SoC) design excellence.
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