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Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design
December 1, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.
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Ansys 2025 R2 Enables Next-Level Productivity by Leveraging AI, Smart Automation, and Broader On-Demand Capabilities
07/30/2025 | PRNewswireAnsys, now part of Synopsys, announced 2025 R2, featuring new AI-powered capabilities across the portfolio that accelerate simulation and expand accessibility.
Target Condition: The 5 Ws of PCB Design Constraints
07/29/2025 | Kelly Dack -- Column: Target ConditionHave you ever sat down to define PCB design constraints and found yourself staring at a settings window with more checkboxes than a tax form? You’re not alone. For many designers—especially those newer to the layout world—the task of setting up design constraints can feel like trying to write a novel in a language you just started learning.
Zuken to Showcase Defence & Security-Focused Electronic Systems Design Solutions at DSEI 2025
07/24/2025 | ZukenZuken, a global leader in electronic and electrical design automation, will showcase its latest innovations for defence and security systems at DSEI 2025, taking place at ExCeL London from 9–12 September 2025.
Creating a Design Constraint Strategy
07/24/2025 | I-Connect007 Editorial TeamMost designers learn how to set their design constraints through trial and error. EDA vendors’ guidelines explain how to use their particular tools’ constraints, and IPC standards offer a roadmap, but PCB designers usually develop their own unique styles for setting constraints. Is there a set of best practices for setting constraints? That’s what I asked Global Electronics Association design instructor Kris Moyer, who covers design constraints in his classes.
Elementary Mr. Watson: Closing the Gap Between Design and Manufacturing
07/23/2025 | John Watson -- Column: Elementary, Mr. WatsonModern PCB designers are not merely engineers or technicians. I believe that PCB design, at its core, is an art form, and modern PCB designers should be considered artists. Beyond the technical calculations and engineering rules lies a creative process that involves vision, balance, and a passion for what we do. Like any artist who works with brush and canvas or chisel and stone, a PCB designer shapes invisible pathways that bring ideas to life. Each trace, layer, and component placement reflects thoughtful decisions that blend form, fit, and function.