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Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design
December 1, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.
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Julia McCaffrey - NCAB GroupSuggested Items
Setting Design Constraints Effectively
07/31/2025 | Stephen V. Chavez, Siemens EDAPCB design requires controlling energy within the medium of a PCB. The manner in which we control the chaos of energy is by implementing and utilizing physical and electrical rules, known as constraints, along with a specific structure and material(s) that make up what is known as the foundation of the design. These rules govern everything within the PCB structure and generally fall into two camps: performance and manufacturability. Setting this foundation correctly is extremely important and the key to success.
MacDermid Alpha Electronics Solutions Unveils Unified Global Website to Deepen Customer, Talent, and Stakeholder Engagement
07/31/2025 | MacDermid Alpha Electronics SolutionsMacDermid Alpha Electronics Solutions, the electronics business of Elements Solutions Inc, today launched macdermidalpha.com - a unified global website built to deepen digital engagement. The launch marks a significant milestone in the business’ ongoing commitment to delivering more meaningful, interactive, and impactful experiences for its customers, talent, and stakeholders worldwide.
Ansys 2025 R2 Enables Next-Level Productivity by Leveraging AI, Smart Automation, and Broader On-Demand Capabilities
07/30/2025 | PRNewswireAnsys, now part of Synopsys, announced 2025 R2, featuring new AI-powered capabilities across the portfolio that accelerate simulation and expand accessibility.
Connect the Dots: Sequential Lamination in HDI PCB Manufacturing
07/31/2025 | Matt Stevenson -- Column: Connect the DotsAs HDI technology becomes mainstream in high-speed and miniaturized electronics, understanding the PCB manufacturing process can help PCB design engineers create successful, cost-effective designs using advanced technologies. Designs that incorporate blind and buried vias, boards with space constraints, sensitive signal integrity requirements, or internal heat dissipation concerns are often candidates for HDI technology and usually require sequential lamination to satisfy the requirements.
Target Condition: The 5 Ws of PCB Design Constraints
07/29/2025 | Kelly Dack -- Column: Target ConditionHave you ever sat down to define PCB design constraints and found yourself staring at a settings window with more checkboxes than a tax form? You’re not alone. For many designers—especially those newer to the layout world—the task of setting up design constraints can feel like trying to write a novel in a language you just started learning.