-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueSoldering Technologies
Soldering is the heartbeat of assembly, and new developments are taking place to match the rest of the innovation in electronics. There are tried-and-true technologies for soldering. But new challenges in packaging, materials, and sustainability may be putting this key step in flux.
The Rise of Data
Analytics is a given in this industry, but the threshold is changing. If you think you're too small to invest in analytics, you may need to reconsider. So how do you do analytics better? What are the new tools, and how do you get started?
Counterfeit Concerns
The distribution of counterfeit parts has become much more sophisticated in the past decade, and there's no reason to believe that trend is going to be stopping any time soon. What might crop up in the near future?
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - smt007 Magazine
Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design
December 1, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.
Suggested Items
Robosys, ACUA Ocean + OREC Secure Funding For Collaborative Autonomy Project
12/25/2024 | RobosysAdvanced maritime autonomy developer, Robosys Automation, supported by USV manufacturer, ACUA Ocean, and Offshore Renewable Energy Catapult (OREC), have jointly secured grant funding through Innovate UK.
IPC Announces New Training Course: PCB Design for Military & Aerospace Applications
12/23/2024 | IPCIPC announced the launch of a new training course: PCB Design for Military & Aerospace Applications.
Effects of Advanced Packaging and Stackup Design
12/26/2024 | I-Connect007 Editorial TeamKris Moyer teaches several PCB design classes for IPC and Sacramento State, including advanced PCB design. His advanced design classes take on some really interesting topics, including the impact of a designer’s choice of advanced packaging upon the design of the layer stackup. Kris shares his thoughts on the relationship between packaging and stackup, what PCB designers need to know, and why he believes, “The rules we used to live by are no longer valid.”
Beyond Design: AI-driven Inverse Stackup Optimization
12/26/2024 | Barry Olney -- Column: Beyond DesignArtificial intelligence (AI) is transforming how we conceptualize and design everything from satellites to PCBs. Traditionally, stackup planning is a manual process that can be multifaceted and relies heavily on the designer's expertise. Despite having best practices and various field solvers to optimize parameters, stackup planning remains challenging for complex designs with advanced packaging, several layers, multiple power pours, and controlled impedance requirements.
Spotlight on PEDC: Filbert Arzola
12/19/2024 | Andy Shaughnessy, Design007 MagazineIPC and FED have teamed up to create a new PCB design conference in Vienna, Austria. The Pan-European Electronics Design Conference (PEDC) takes place Jan. 29-30 at the NH Danube City hotel in Vienna. Raytheon’s Filbert Arzola is presenting “Engineering and Adapting Model-based PCB Design in Step with Sustainability and Digital Twins” at PEDC. I asked Filbert to discuss what attendees can expect from his class.