IMAPS Wrap-up: AI, Chiplets, and 3D Cube Architecture

Estimated reading time: 3 minutes

The International Microelectronics Assembly and Packaging Society, IMAPS, held its 20th Device Packaging Expo and Conference this past week in Fountain Hills, Arizona, followed immediately by its Workshop on Advanced Packaging for Medical Electronics that continued through the remainder of Thursday and Friday. Fortunate to find myself in Texas earlier in the week, I made it for the last day of the IMAPS event and attended two excellent keynote presentations by AMD and Intel, respectively.

Though not a core event for our part of the supply chain, I would recommend some of my engineering and materials friends put the IMAPS Device Packaging conference on their calendars for March 2025. As we continue to beat the drum that “chips don’t float,” the visionary tech trends illustrated at this conference should remain in our peripheral vision, at least. Having grown significantly over the past several years, the IMAPS Device Packaging conference will be moving to a larger venue for 2025, at the Sheraton Wild Horse Pass Conference and Event Center in Phoenix, again to be held in March.

The first keynote was presented by Hemanth Dhavaleswarapu of AMD, with a presentation entitled Enabling Heterogenous Integration through Chiplet Architecture. He began his talk by emphasizing the importance of “AI Driving Computer & Memory Growth” per his first slide, which featured three staggering growth charts devoted one each to AI computing, AI supercomputers and performance, and AI memory. He proceeded to discuss IO bandwidth concerns related to the requirement to accommodate signal speeds up to 100G in the next generation of accelerators and traditional scaling challenges.

And then, the packaging discussion began. Mr. Dhavaleswarapu took us through a chiplet journey from 2015 to the present with 2022 and 2023 highlighting innovative packaging using hybrid bonding and Wafer on Wafer stacking culminating in what will eventually need to be 3D packages to accommodate a less than 10-micron pitch. He spoke of the need for chiplets packaging to work together, “Multi variant (APU/XPU) architecture requires all chiplets to act as if they are LEGO building blocks.” Ultimately though, he pointed out, choosing packaging architecture will be based on a balance of power, performance, and cost. AMD is indeed working on impressive technology in its next-generation chips.

Pooya Tadayon of Intel followed with his presentation, Advance Packaging: Enabling the Future of Moore’s Law, reinforcing that we are, indeed, there. Simplified a bit from the previous presentation, Mr. Tadayon cited the main technology drivers as wafer cost and performance or scaling. He also took the audience through an evolution of advanced packaging over time, landing on an aspirational 3D Cube architecture, something he freely admitted would not happen this decade, perhaps not even in the next. The main points of his presentation are summarized by his following statements. “The era of 3D integration and advanced packaging is upon us, but the ecosystem is not ready,” while reminding us that necessity has always been the mother of invention. And metrology, physical debugging, and manufacturing testing are huge challenges that may allude us for some time. Further, he put out a call to action to the young, great brains in the room to solve these issues and more as we push forward. This technology will require new and more discipline integrative tools in almost every area of manufacturing and test.

Honestly, some of the figures shared at the IMAPS Device Packaging conference were nothing short of mind-blowing and provided quite a perspective in the bigger scheme of things. Colleagues with whom I spoke just after the presentations agreed.

One thing is very clear— all parts of the electronics supply chain are becoming ever more dependent on one another’s success to move to the next level. Collaboration, standards, young, creative minds who are less daunted by the challenges we old dogs have grappled with since the dawn of the first transistor— will lead us to what is, today, an impossible technological dream.