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iNEMI Packaging Tech Topic Series: Damage-Free Rapid Electron Beam Testing for Advanced Packaging
July 24, 2024 | iNEMIEstimated reading time: 1 minute
Testing issues are limiting chip makers’ ability to create larger SOCs (system-on-chip). The scan field dimensions of EUV (extreme ultraviolet light) and NA (numerical aperture) EUV, which are typically used for testing, are too small. To enable larger chips, manufacturers are migrating to system-on-a-package (SOP). This transition requires segmenting the final chip into many chiplets/tiles and reassembling the components using a combination of interposers, base tiles, EMIBs and substrates.
The active chiplets/tiles, such as CPU cores, GPUs, memory and I/Os, are tested the same as SOCs, with advanced logic testers and BIST (built-in self-test). BIST is made possible by the active silicon within the chiplets/tiles. The interposers, base tiles, EMIBs and substrates, which are the building blocks of SOPs, lack the active silicon to make traditional testing possible. To test these foundational building blocks of SOP, massive electrical contacting arrays of probes have been used. This method is slow, expensive, inflexible, and worst of all, can damage the device under test.
Applied Materials’ Yield Technology Group (YTG) has developed a non-contacting electron beam tester to enable testing of SOP building blocks. This presentation will introduce the Applied Materials damage-free electron beam testing method that can ensure high yield of SOP building blocks.
About the Speaker
Peter D. Nunan
General Manager Emeritus
Yield Technology Group, Display & Flexible
Technology Group
Applied Materials, Inc.
Peter D. Nunan spent 30+ years in semiconductor yield improvement. He started at Bell Laboratories in 1979, working on semiconductor yield equipment. In 2014, he assumed the role of General Manager of the Applied Materials Display Yield Technology Group (2014 to 2024). The stated objective of YTG is to bring semiconductor yield methods and equipment to the display and advanced packaging industries. The group’s goal is to enable display and advanced packaging manufacturers to develop and produce advanced displays, interposers and substrates. Prior to joining Applied Materials, Peter held various positions within the semiconductor industry, including Vice President of Varian Semiconductor Technology Development and Vice President-General Manager of KLA-Tencor’s Professional Services Division.
Registration
This webinar is open to industry; advance registration is required (see link below).
August 6, 2024
9:00-10:00 a.m. EDT (Americas)
3:00-4:00 p.m. CEST (Europe)
10:00-11:00 p.m. JST (Japan)
Register for this webinar
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08/01/2024 | iNEMITesting issues are limiting chip makers’ ability to create larger SOCs (system-on-chip). The scan field dimensions of EUV (extreme ultraviolet light) and NA (numerical aperture) EUV, which are typically used for testing, are too small.