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Suggested Items

Every Layer Interconnect: The Promise, the Pain, and the Practical Limits

07/02/2026 | Anaya Vardya, American Standard Circuits
Every layer interconnect (ELIC) is an architectural statement about how a PCB is built, signaling a fundamental shift in how we think about routing density, vertical interconnect, and the relationship between design and fabrication. To understand what ELIC solves, you have to understand what it replaces. Traditional HDI construction uses a rigid core with sequential build-up layers on one or both sides:configurations such as 2-4-2 or 3-2-3.

Base Material Properties and Microvia Reliability

07/01/2026 | Ed Kelley, Victory Giant Technology
The drive toward higher circuit density is challenging PCB manufacturers and their supply chains alike, with base materials as a critical foundation for complex designs. HDI designs present specific challenges and requirements for these materials, but given the myriad possible designs and applications, there is no optimal “one size fits all” material. Perhaps the most challenging HDI designs are those that use stacked vs. staggered microvias, with the number of layers of stacked microvias and the pitch between them as critical variables.

Thermoreflectance and Solving the Thermal Puzzle in 3D Packaging

06/11/2026 | Marcy LaRont, I-Connect007
Advanced packaging and 3D heterogeneous integration are rapidly redefining the next phase of the semiconductor industry, delivering unprecedented performance gains while posing significant thermal management challenges. In this interview, Dr. Mohammad (Mo) Shakouri, founder and CEO of Microsanj, discusses how thermoreflectance-based metrology is enabling engineers to visualize and measure heat behavior at the nanoscale within complex packages, interposers, and TSV structures.

OKI Develops 180-Layer, 15 mm PCB for AI Semiconductor Test Equipment

04/29/2026 | BUSINESS WIRE
OKI Circuit Technology, the OKI Group’s printed circuit board (PCB) business company, has successfully developed design and production technologies for 180-layer, 15 mm-thick PCBs intended for use in wafer testing equipment for high bandwidth memory (HBM) mounted on AI semiconductors.

Target Condition: An Exploration of Flooding PCB Layers

04/02/2026 | Kelly Dack -- Column: Target Condition
The concept of flooding PCB layers with copper has been around for so long, you’d think we’d have it mastered. We haven’t. (Oh, and by “we,” I mean design engineers and the software tools we depend on.) Years ago, PCB artwork was created by hand using light tables, with tape applied to Mylar. Signals were slow, traces were relatively wide, and high-current paths were simply “beefed up” with wider copper. Signal integrity wasn’t yet a driving concern. Today, solid return paths are fundamental to robust design. We understand the importance of continuous reference planes for signal integrity and EMI control.
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