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Happy’s Tech Talk #35: Yields March to Design Rules

Ultra high density interconnect (UHDI) has many forms, structures, and alternatives, so capturing all the variations and reducing them to design rules has required some departures from traditional IPC design standards. In this column, I’ll be discussing the IPC UHDI design guidelines and standards.

What Drives Yields?
The fundamental question is: “Do you need HDI or microvias?” IPC-2315, Design Guide for High Density Interconnects and Microvias, helps answer that question by providing wiring demand estimates. If HDI is required (or desired), the document walks you through the design process: selection of critical HDI dielectrics from IPC-4104, Specification for High Density Interconnect (HDI) and Microvia Materials; selection of blind and buried via structures; and selection of design rules.

The design rules and structures in the standard are arranged in increasing degrees of complexity, starting with a single build-up layer of microvias and drilled through-holes throughout the entire structure. This is a Type I structure. Type II is a single HDI layer over a two-sided or multilayer core. Therefore, it has buried vias. The next section introduces variations in the structure by allowing stacked vias, variable depth vias, and conductive paste vias. The last section applies to two or more build-up layers over a core—Type III. If fabricated sequentially, the last set of surface blind vias becomes buried vias as they are covered by the last HDI layer.

A key concern during the development of these design rules was being able to capture the diversity of capabilities of fabricators and the interaction of design rules and structures that cause abnormally poor yields. As a committee, we finally decided that the best way to illustrate this large variability was to classify the minimum geometries into four design categories from A–D. Any known poor design practices of the design rules would be called out as a warning. Table 1 shows a sample of a design rule for a Type II HDI structure, with examples for Category D from IPC-2315 and Level C from IPC-2226A, Sectional Design Standard for High Density Interconnect (HDI) Printed Boards. Revision B for IPC-2226 will be released soon.

The IPC committee working on these standards had concerns that these design rules were based on the reported capabilities of fabricators and the needs expressed by OEM board designers. But what of yields and cost? You can claim any design rules, but can you build it? This concern may now have a solution.

Ron Rhodes and Tim Estes of Conductor Analysis Technologies, Inc. (CAT) have developed process characterization coupons for basic PCB fabrication processes. They wrote2 about these coupons and provided many reports about how this is used to characterize production, set design rules, qualify vendors, and function as responses for design of experiments (DOE). Their current coupons have been designed to measure the capability of HDI fabrication and can be adapted to UHDI. With this tool, I see the need to use these coupons and panels to measure the yields, interactions, and capabilities of HDI and UHDI processes and design rules that we have put in IPC standards. The capability of different HDI processes can then be compared to the levels A–C (Figure 1).

Figure 1 starts with the bottom box—the characterization of manufacturing capabilities. By using the CAT coupons, mean standard deviations and process capability (Cp and Cpk) can be statistically determined. The performance provides data for acceptability and requirements specifications. Both need to be related to the design rule nominals and tolerances proposed in IPC-2226A. This scenario then provides the settings for CAM’s manufacturability review and design rule checking.

Tying design rules to fabrication performance can help us better understand costs. Tight design rules are no good if no one can build them. For those who can, the designer needs to be pre-warned that yields could be quite low and costs correspondingly higher. This might be tolerable for the designer, provided he is willing to pay.

Summary
The need for the PCQRR program is great. I had the chance to see it in action at the Taiwan High-Tech Forum at IPC APEX EXPO 2024. The next step is to tie our HDI and UHDI manufacturing processes to the new IPC HDI design standards and then to IPC UHDI design standards. Contact IPC if you want to participate or if you support such a program.

References

1. IPC-2315 and IPC-2226A, ipc.org.
2. “Understanding Process Capability, Quality, and Reliability,” by Tim Estes, Ronald Rhodes, and David Wolfe, HDI Handbook, Conductor Analysis Technologies, Inc., 2010.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. 

This column originally appeared in the November 2024 issue of PCB007 Magazine.