Estimated reading time: 2 minutes

The Shaughnessy Report: Watt About Power Integrity?

Yes, that headline is the equivalent of a dad joke, but editors can’t pass up a chance to inject a little humor into a headline, and I had to take my shot. 

Power integrity (PI) problems are no joke. Current power demands are increasing, especially with AI, 5G, and EV chips, which can lead to voltage drops that kill your performance.

This can be ameliorated with wide trace widths and solid plane design, but space requirements are a constant tradeoff. In fact, much of PI is a game of tradeoffs. Adding thicker traces and additional layers can increase performance, but this also increases manufacturing cost as well.

As always, a little planning goes a long way: Get to work optimizing the power delivery network early on, setting impedance targets and designing the perfect stackup. EMI is more likely with these fast-switching power circuits, but solid ground planes with stitching vias can help fight EMI, as well as ground bounce.

Unlike signal integrity, there isn’t a mountain of published content devoted to PI design techniques. The PCB design community has been focused on signal integrity since the 1990s, when dropping IC rise times and rising clock speeds started causing impedance and EMI issues and forced designers to address the issue.

But PI wasn’t a big problem for most PCB designers until the 2000s, when power-hungry chips and features likewise forced the industry to take notice. One of the first things that the PI “pioneers” noticed was that most SI tools were not a big help with PI. Luckily for designers, PI software tools are readily available now, but achieving accurate measurements can be tricky. And while simulation and analysis tools can smooth out the process, they also increase the design cycle.

As technologies such as chiplets and 3D-IC continue to proliferate, solid knowledge of PI design techniques will become a critical tool in your toolbox. This month, our experts share “watt’s up” with power integrity, from planning and layout through measurement and manufacturing.

Our featured contributors include Heidi Barnes of Keysight Technologies, Istvan Novak of Samtec, Zach Caprai of Siemens EDA, and columnists John Watson, Barry Olney, Kelly Dack, and Vern Solberg. We have a column by Matt Stevenson, and another article in a series by Anaya Vardya. Beth Massey of MacDermid Alpha Electronics Solutions discusses various potting compounds that can help manage issues such as CTE mismatch in RF applications.

See you next month!

This column originally appeared in the October 2025 issue of Design007 Magazine.