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The Knowledge Base: The Era of Advanced Packaging

The semiconductor industry is at a pivotal juncture. As the traditional scaling predicted by Moore's Law encounters significant physical and economic barriers, transistor density can no longer double every two years without escalating costs and complications. As a result, the industry is shifting its focus from chip-level advancements to innovative packaging and substrate technologies. This evolution is driving the exploration of advanced packaging techniques, such as 2.5D and 3D architectures, and chiplet designs, all of which offer new avenues to continue performance improvements and overcome the limitations of traditional scaling.

Advanced packaging has emerged as a critical enabler in this new era, allowing multiple chips to be integrated within a single package, thereby enhancing performance, power efficiency, and overall system reliability. By stacking chips vertically or placing them side by side in a more connected manner, these technologies significantly reduce power consumption, improve data transfer speeds, and enable greater functionality within a smaller footprint. This shift is not just about overcoming the limits of Moore's Law but redefining how electronic systems are designed and manufactured, setting the stage for continued innovation in high-performance computing and beyond.

I Invited Dr. Nava Shpaisman, strategic collaboration manager at KLA, to provide some insight.

How do you see Moore's Law evolving in the context of advanced packaging technologies?

Dr. Nava Shpaisman: Moore’s Law, which predicted transistor density to double every two years, has guided the industry for decades. However, shrinking transistors to minuscule sizes is no longer sustainable due to high costs and physical limitations. As leading-edge node architecture becomes more complex, integrating multiple dies into a single package becomes crucial.

Advanced packaging provides designers with a solution to overcome these limitations by arranging multiple chips in three-dimensional structures and creating direct connections between them. An added advantage is the ability to place chips with different functions close to each other, resulting in increased speed and reduced power consumption and cost. By simplifying multi-function devices into a single package, we can continue improving chip performance without solely relying on transistor size reduction.

In addition to improving performance, power distribution and interconnect density, heterogeneous integration has also proven to be a cost-effective method for integrating multiple functions in packaging instead of on a wafer. With updated 2.5D and 3D architectures serving various end-applications, heterogeneous integration continues to accelerate, opening endless possibilities. It’s also making it more challenging to attain reliable electrical connections between different components with varying process technologies.

What are the key challenges that the industry faces in this transition to advanced packaging?

Moving to advanced semiconductor packaging involves several key areas. Components are shrinking and becoming more powerful, so managing heat dissipation becomes critical. Efficient thermal solutions prevent overheating and ensure long-term reliability. Smaller components demand finer pitches and tighter spaces. Ensuring robust interconnects while avoiding signal integrity issues in densely packed designs is a challenge. Integrating diverse materials

(dielectrics, metals, and substrates) can cause reliability issues due to differences in coefficients of thermal expansion (CTE), making compatibility and reliability across material interfaces essential.

Handling ultra-thin substrates without compromising mechanical strength adds another layer of complexity. Advanced packaging techniques involve complex processes, increasing manufacturing costs; achieving high yields during production is crucial for cost management. Validating complex packages requires advanced testing methods, and ensuring reliability throughout the product's lifecycle remains a persistent challenge. Lastly, the availability of specialized materials, equipment, and skilled personnel impacts the scalability and adoption of novel packaging technologies.

Can you explain the significance of moving from traditional chip scaling to advanced packaging methods, such as 3D stacking and chiplet architectures?

While semiconductor chip transistor density increases, efficiency gains flatten. As Moore's Law scaling slows down, designers are turning to advanced packaging to continue performance improvements in end applications.

The simplest integration level is 2D, where multiple chips are placed side-by-side on a common substrate (usually a silicon wafer or organic substrate). Through the combination of multiple dies on a silicon interposer, 2.5D architectures provide electrical connectivity between the dies. Higher interconnect density is required for shorter signal paths.

The industry is shifting toward advanced packaging methods, such as 2.5D and 3D packaging. The key to advanced packaging is heterogeneous integration, where multiple functions originating from different chip technologies are integrated together in a single package.

3D packaging involves vertically stacking multiple dies using TSVs (through silicon vias) to create a true 3D stacking structure. This will reduce the form factor and data transfer distances and improve the overall system performance.

Chiplet architecture, on the other hand, breaks down a large chip into smaller, modular chiplets that can be combined in a single package to create a custom solution. This approach allows for increased flexibility and scalability, as chiplets can be mixed and matched to meet the specific needs of a particular application.

By using chiplets—small, modular chips that can be combined in various configurations—manufacturers can create highly customized and powerful high-performance computing (HPC) solutions. This approach not only improves performance but also reduces costs and development time.

These innovative packaging technologies invite novel ways to add more functions and optimize interconnect densities. They bring chip functions physically closer together to unlock computing, latency, and power advantages.

Overall, the industry is shifting from the system-on-chip concept to system-of-chips through disaggregation of functions previously built on a single die.

How do you think the shift from chip-centric to package-centric design impacts the overall performance, power efficiency, and reliability of electronic systems?

Today’s advanced graphics processing units (GPUs) are a great example of how heterogeneous integration makes possible the high-performance architecture that’s essential for delivering AI-caliber computing power.

GPU memory has grown by 16X over the past decade. This was achieved through high-bandwidth memory-dynamic random-access memory (HBM)–DRAM) chips stacked on top of each other. Using advanced packaging, GPU packages integrate GPU processor chips and multiple stacked HBM memory modules in proximity inside the same package.

The challenge for packaging designers is balancing performance with power efficiency, and reliability. As we continue to see innovation accelerated in heterogeneous integration with new 2.5D and 3D architectures, the industry is developing more efficient ways to achieve high interconnect density to meet performance and cost requirements.

Heterogeneous integration methods include hybrid bonding, embedded bridges, wafer and panel interposers, glass core substrates, and, in the long term, co-packaged optics. Each of these delivers breakthroughs in packaging interconnect density for chips targeting high-performance apps. However, they also pose new process and process control challenges across wafer-level packaging, assembly, and substrate manufacturing.

Many of the advancements achieved in packaging will also target the substrate and panel-level. For example, to support more connectivity over a smaller surface, advanced substrates are characterized by high layer count, large unit size, and fine lines. IC substrates (ICS) pose unique challenges for manufacturers, specifically when it comes to patterning large unit size, high layer count, fine-line build-up film substrates of uneven topography.

In the shift to package-centric design, ICS manufacturing yield is key to achieving breakthroughs in performance, power efficiency, and reliability of electronic systems. ICS manufacturers that want to accelerate their yield curve need to adopt increasingly high sensitivity for inspection, customized to account for different handling, noise sources, warpage, and thicknesses found in packaging applications.

For manufacturers seeking leadership in packaging innovation, there is a significant opportunity to bridge methodologies across the three worlds of front end, packaging, and substrates.

KLA’s process and process control methodologies bring the precision of front-end semiconductor manufacturing to the dynamic realm of customized packaging. Manufacturers need front-end-like inspection and metrology capabilities, which is what KLA provides.

What role do materials science and substrate innovations play in the future of semiconductor packaging, and which materials are currently leading the way?

Materials science and substrate innovations are crucial in advancing semiconductor packaging technology. Choosing the right materials requires balancing performance, reliability, and cost. Some advanced packaging materials include low-loss materials, which are crucial for high-frequency and high-speed applications. For mechanical stability and warpage prevention, these materials must maintain a high Young’s modulus.

While choosing the set of materials comprising the package, such as dielectric, molding compound, soldering material, etc., designers and manufacturers must match the coefficient of thermal expansion (CTE) to the silicon die, to avoid structural failures such as fracture and cracking within the packaging during thermal processes.

In choosing among silicon, organic, or glass interposer materials, performance, reliability, and cost must be considered. While silicon interposers offer excellent electrical performance and thermal conductivity and can be expensive and prone to warpage, organic interposers are cost-effective and have a better CTE match with the substrate, but with lower thermal conductivity. Glass interposers have superior electrical performance and a CTE closer to silicon. However, they are fragile and require specialized manufacturing processes.

Lastly, alternative bonding materials, such as bumping and Cu pillars, enable smaller pitch sizes. Through-silicon vias (TSVs) allow stacking dies vertically. However, there are challenges to consider, such as thermal management, reliability, electromagnetic interference (EMI), cost-effectiveness, and supply chain stability.

How does the trend of integrating more components within a single package influence thermal management, and what innovations are being developed to address these challenges?

It is possible to shorten signal paths and still properly dissipate heat on a single die. However, multiple dies in a package require thinner substrates and dielectrics to ensure that signals travel fewer distances, which reduces thermal dissipation.

Materials with similar CTEs minimize these stresses, reducing premature failure risks and other thermally induced effects, such as accelerated aging, reduced electron mobility, or analog or optical signal drift.

Heterogeneous integration requires a fundamental understanding of the thermal expansion properties of every material. This could ultimately affect the packaged device's reliability and yield. That’s only part of the problem. Advanced packaging requires an understanding of what else is near a chip or chiplet, and how those other elements are used. All of that needs to be modeled and simulated together using a realistic workload. Changes in computing requirements complicate this problem. For example, in data centers where generative AI has significantly increased the amount of data to be processed, the result is higher processor and memory utilization.

To achieve 3D IC integration, several key technologies are required, such as TSV, wafer thinning, and wafer/chip bonding. These technologies are important in providing thermal and electrical pathways between layers. 3D integration relies on TSV because it reduces package size and shortens the interconnection path. It allows shorter chip-to-chip interconnections and a minimum pad size and pitch.

With components becoming both larger (e.g., for higher performance) and smaller (e.g., for IoT devices), how do you foresee packaging technologies adapting to this dual demand?

Semiconductor packaging technologies are evolving rapidly to meet the dual demand for larger, high-performance components and smaller, more efficient ones for IoT devices. We are seeing several key architectural approaches.

Technologies like 2.5D and 3D packaging, fan-out wafer-level packaging (FOWLP), and system-in-package (SiP) improve performance while maintaining a compact form factor.

Heterogeneous integration reconciles the dual demand for enhanced performance and compact form-factor. This approach combines different types of chips (e.g., logic, memory, sensors) within a single package. It enables the creation of multifunctional devices that are both powerful and small, ideal for IoT applications.

Flip-chip and wafer-level packaging offer higher interconnect density and better electrical performance compared to traditional wire bonding. They are crucial for high-performance applications and are also adaptable for smaller devices. For IoT devices, the focus is on reducing size and power consumption. Advanced packaging technologies are enabling the production of ultra-small, energy-efficient chips that can be embedded in a wide range of devices.

These advancements are helping the semiconductor industry balance the need for both high performance and miniaturization, driving innovation across various applications from consumer electronics to industrial IoT.

FOWLP and FOPLP are two packaging technologies gaining traction recently. What are some of the drivers and challenges for these approaches?

With the surge in data-hungry applications like AI, where chips are larger, fan-out panel-level packaging (FOPLP) technology is gaining renewed attention. By utilizing larger panels instead of wafers, such as 600-mm square panels, compared to traditional 300-mm round wafers, manufacturers can achieve significant cost reductions and boost production efficiency.

Packages can be built in two ways. A foundry must decide whether to use the chip-first or chip-last method. The chip-first/RDL-last approach reduces process steps and production costs. Whereas a chip-last/ RDL-first approach reduces risk of damaging an expensive AI chip since its pads and RDLs are inspected and checked. When a bridge is used to connect mounted dies, both methods will probably be used: chip-first for the cheapest bridge and chip-last for the AI die.

Moving to panel-level packaging raises several challenges, some of which are associated with the transition to panels, while others are also relevant to wafer-level packaging (WLP), but with amplified effects. One of the primary challenges is die shift (bridge), which can occur during the manufacturing process and lead to misalignment, affecting the overall performance of the package.

Warpage of panels after molding and redistribution layers (RDLs) is another major issue. Warpage can cause difficulties in handling and transporting the panels, misalignment in the bumping, and potential defects. Due to the large size of the panels, handling and transport are challenging. Ensuring uniformity across the entire panel, especially for processes like coating, sputtering, and plating, is also critical.

Looking ahead, what do you envision as the next major breakthrough in semiconductor packaging, and how might it redefine the way we think about electronics design?

Co-packaged optics (CPO) is an innovative technology that integrates optics and silicon in a single package. It addresses bandwidth and power challenges in next-generation data centers and cloud infrastructure. CPO combines expertise in fiber optics, DSP, switch ASICs, and advanced packaging and testing, to provide a disruptive system value. Copper interconnects are reaching their limits, and silicon photonics offer a solution with higher speed, longer reach, reduced latency, and energy efficiency.

This integration minimizes signal loss and power consumption, leading to faster data transfer rates and lower energy usage. CPO also provides increased scalability and design flexibility, allowing for the integration of multiple optical and electronic components within a single package. This is crucial for meeting data centers' growing demands.

Effective thermal management is a critical challenge in semiconductor packaging. By integrating optical components, CPO improves heat dissipation. The adoption of CPO is being driven by major industry players, and the technology is expected to grow significantly in the coming years. However, there are also challenges, including manufacturing complexity and the need for specialized equipment and materials. Addressing these challenges will be crucial for CPO implementation and widespread adoption.

This column originally appeared in the December 2024 issue of SMT007 Magazine.