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Raytheon Wins Contract to Advance Next-Gen Software-Defined Radar

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PCB East 2026: AI Infrastructure, Advanced PCB Technologies, and the Future of Electronics Manufacturing

05/19/2026 | Doug Dixon, 360Circuits
After attending PCB East 2026, it became clear to me that the electronics industry is entering a major transition driven by AI infrastructure, increasing power density, and growing system complexity, extending far beyond semiconductors alone. What stood out was how critical PCB technology, materials science, thermal management, and advanced manufacturing have become to the future of electronics. The industry is now facing many challenges, including tighter manufacturing tolerances, material shortages, rising costs, and growing pressure to digitally transform engineering and manufacturing operations.

Marcy’s Musings: Additive Processes, Signal Consequences

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What Heterogeneous Integration Means for EMS Providers

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Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.

System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor

05/14/2026 | Chetan Arvind Patil, Marvell Technology
In conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
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