DuPont to Showcase Advanced Semiconductor Wet Etching Innovations at the Surface Preparation and Cleaning Conference
May 13, 2025 | DuPontEstimated reading time: 2 minutes
DuPont announced that it will present its latest developments in semiconductor wet etching technologies at the upcoming Surface Preparation and Cleaning Conference (SPCC) in Chandler, Arizona, beginning May 20.
Continued growth in advanced computing and AI is driving demand for data storage in servers, solid state drives and consumer electronics. As semiconductor fabricators develop faster and more power-efficient next-generation memory chips to support these applications, there are numerous technical challenges including shrinking design rules, narrower feature sizes and higher aspect ratios. Novel wet etching processes are emerging as a key enabler for 3D NAND flash memory design, requiring new etchant materials.
“DuPont has been working closely with leading semiconductor fabricators to understand emerging challenges and requirements in selective etching processes,” said Young Bae, global business director, Advanced Cleans & Slurry Technologies, DuPont. “By leveraging our core competencies in selective cleaning technologies, we have successfully expanded our product offerings to feature high selectivity etchants including selective molybdenum etchants.”
One example of where novel etchants are being used is supporting the vertical extension of 3D NAND memories that contain more layers of alternating tungsten word lines and dielectrics. As this taller structure presents significant challenges for the dry etching process of high aspect ratio channels and interconnects, there has been a shift toward vertical densification with thinner word lines using molybdenum as an alternative for tungsten. Since traditional etching processes developed for tungsten word lines are not applicable for molybdenum word lines, it is critical to create high selectivity etchants specifically for molybdenum. DuPont’s developments can also enable combining the etching and cleaning processes into a single step, streamlining the process while improving performance and extending the lifespan of the etchant bath and its shelf life.
At SPCC, DuPont’s experts will present technical sessions to share advancements in a new molybdenum etchant that is designed with a multi-dissolver system to enhance the dissolution of molybdenum oxides, improving top-to-bottom etch uniformity for 3D NAND fabrication. DuPont representatives will also present developments in a high selectivity silicon etchant that offers high etch rates and excellent compatibility with silicon-germanium for backside power delivery network applications. This research is informing new product development for DuPont’s EtchSolv™ precision etchant family.
“We are excited to share our latest research in high selectivity etchants for advanced semiconductor manufacturing at SPCC,” said Bae. “Precision etching materials will contribute to the overall performance, efficiency, and reliability of advanced semiconductor devices, particularly in areas like 3D NAND/3D DRAM technology, where vertically stacked memory cells are essential for achieving greater density and faster performance.”
DuPont will have an exhibit booth at SPCC to discuss EtchSolv™ etchants and semiconductor cleans.
Subscribe
Stay ahead of the technologies shaping the future of electronics with our latest newsletter, Advanced Electronics Packaging Digest. Get expert insights on advanced packaging, materials, and system-level innovation, delivered straight to your inbox.
Subscribe now to stay informed, competitive, and connected.
Suggested Items
Institute of Circuit Technology Spring Seminar 2026: A Bright Future in Europe
04/23/2026 | Pete Starkey, I-Connect007Through the leafy lanes and spring flowers of Warwickshire and back to Meridan, the traditional centre of England, and now officially part of the Metropolitan Borough of Solihull in the county of the West Midlands, I attended the Annual General Meeting and Spring Seminar of the Institute of Circuit Technology (ICT) on April 14. Out of the AGM came notable changes in leadership at the top of the Institute: the retirement of Mat Beadel as chair and Emma Hudson as technical director. Effective May 1, Steve Driver is the new chair, and Alun Morgan is the new technical director.
Henger Targets AI PCB Challenges With Advanced Plasma Technology
04/02/2026 | I-Connect007 Editorial TeamHenger is pushing the boundaries of PCB manufacturing with its dynamic, next-generation plasma technology, purpose-built for the demands of AI-driven electronics. As designs move toward higher density, faster speeds, and advanced materials like M9 laminates, Henger’s innovative plasma systems deliver precise, uniform, and energy-efficient processing. In this interview, company leaders, Zhiquang Li and Ping Tang discuss how their cutting-edge solutions are redefining cleaning, surface activation, and process control—positioning plasma technology as a critical enabler of reliability and performance in the rapidly evolving AI hardware landscape.
New, Greener Solutions for Etch: Novel Copper Extraction
03/30/2026 | Richard Nichols, GreenSource Engineering“Novel” is a typical marketing phrase that implies new and unique, but often “novel” actually means an established technology being applied to a new field or application. This, in turn, is often driven by newly relevant external motivation. GreenSource has been working on just such a solution: novel copper extraction, offering a better and greener alternative to traditional LLE control systems for cupric chloride etch.
Connect the Dots: Designing for the Future of Manufacturing Reality—Strip-Etch-Strip
02/19/2026 | Matt Stevenson -- Column: Connect the DotsThe demand for ultra-high density interconnect (UHDI) PCBs is growing as electronic devices become increasingly advanced. That means we will be creating more designs that need to align with the reality of manufacturing UHDI boards. My last column on this subject focused on plating, and we are ready to discuss the strip-etch-strip (SES) process. With UHDI boards, footprints are smaller and tolerances are tighter. Your big design challenge associated with the SES process involves trace width and spacing control. The etching process can undercut traces and alter their final size.
PCBAIR Upgrades Heavy-Copper PCBs to Solve AI Thermal Bottlenecks
01/20/2026 | PRNewswireAs computational demands for AI models surge, the hardware powering them faces a critical physical limitation: thermal management.