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Promex Industries CEO Richard Otte Honored with IEEE Electronics Manufacturing Technology Award
May 27, 2025 | PromexEstimated reading time: 2 minutes
Promex Industries, Inc., a Silicon Valley-based provider of advanced design, packaging, and microelectronics assembly services, today announced that CEO Richard (Dick) Otte has received the 2025 Electronics Manufacturing Technology Award from the IEEE Electronics Packaging Society (EPS). The annual award recognizes individuals who have made impactful, sustained contributions to the field over 15 years or more, such as leading the development of major new processes in electronic manufacturing or significantly improving the yield or reliability of established processes.
“Our selection committee was very pleased to give this year’s award to Dick Otte,” said Dr. Patrick McCluskey, EPS program director, awards program. “His contributions are widely known and admired throughout our industry. From helping drive creation and advancement of the Heterogeneous Integration Roadmap, to heightening awareness of U.S.-based packaging and assembly capabilities, Dick has been a great champion for our sector and its importance for advanced electronics.”
Otte has dedicated more than five decades to advancing electronics packaging, shaping the industry with groundbreaking innovations. One of his earliest achievements was leading the development and introduction of multichip modules (MCMs) at Advanced Packaging Systems in the ’90s, laying the foundation for increasingly sophisticated packaging techniques. Building on that success, Otte continued pioneering methods for creating smaller, denser, and more complex assemblies that integrated semiconductor die alongside non-electronic components—an approach that marked the beginning of heterogeneous integration.
His contributions included supporting industry technical roadmaps: IEEE International Technology Roadmap for Semiconductors (ITRS), IEEE Heterogeneous Integration Roadmap (HI), and the iNEMI and International Photonic System Roadmaps (IPSR). The latter anticipated the integration of optical technologies to enhance data rates while reducing power consumption. Through his innovative work, Otte has contributed to advancements that have significantly improved the functionality, efficiency, and reliability of electronic devices across the medical, biotech, communications, and data processing industries—helping shape the future of smaller, smarter, and more dependable technology.
The award will be presented during the EPS Luncheon at the Electronic Components and Technology Conference (ECTC) in Dallas, Texas, on May 29, 2025.
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05/15/2026 | MacDermid AlphaAs volatile silver prices continue to place pressure on semiconductor packaging costs and supply chain predictability, MacDermid Alpha Electronics Solutions will highlight material strategies that help manufacturers reduce dependence on silver without sacrificing reliability, thermal performance, or manufacturing efficiency.
What Heterogeneous Integration Means for EMS Providers
05/14/2026 | Nolan Johnson, I-Connect007Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.
System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor
05/14/2026 | Chetan Arvind Patil, Marvell TechnologyIn conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
I-Connect007 Announces Upcoming Issue of Advanced Electronics Packaging Digest
05/13/2026 | I-Connect007The next issue of Advanced Electronics Packaging Digest examines the materials, architectures, and integration strategies shaping the next phase of electronics innovation, from reinforcement materials under thermal and frequency pressure to heterogeneous integration and advanced packaging as a system-level scaling factor.
ASE, WUS Announce Strategic Collaboration to Build Advanced AI Packaging Hub in Kaohsiung
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