Siemens Collaborates with Samsung Foundry on Advanced Node Product Certifications and EDA Innovation

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Siemens Digital Industries Software announced a significant expansion of its collaboration with Samsung Foundry, including extending certification for many of Samsung’s most advanced process technologies across Siemens’ comprehensive Electronic Design Automation (EDA) portfolio.

These certifications encompass Samsung's cutting-edge FinFET and MBCFET  processes - including 14nm through 2nm nodes (SF2/SF2P) - enabling mutual customers to leverage Siemens' Calibre® software, Solido™ software and Aprisa™ software with confidence when designing next-generation semiconductor devices for manufacture at Samsung Foundry.

Beyond certification, the companies today also unveiled new joint innovations that help customers address critical design challenges in power integrity, silicon photonics, analog mixed-signal reliability verification and other key domains.

"Samsung Foundry is pleased to expand our collaboration with Siemens, which continues to increase its value to the Samsung Foundry ecosystem by offering more functionality in support of our newest advanced processes,” said Sungjae Lee, vice president and head of the Foundry PDK Development Team at Samsung Electronics. “Our work with Siemens also extends beyond product certifications, to include a host of innovative new joint solutions that our shared customers can use to differentiate and win in some of the most competitive and fast-growing industries in the world.”

Advanced node qualifications for Siemens’ Calibre, Solido and Aprisa

Siemens EDA product lines were recently qualified for use with Samsung’s latest FinFET and MBCFET processes, including 14nm through 2nm nodes (SF2/SF2P).

These Siemens EDA product lines include the following:

• Calibre nmPlatform for integrated circuit (IC) verification signoff; and Calibre DesignEnhancer, which takes the Samsung Foundry’s rules and automatically performs layout optimization tasks that enhance customers’ designs.
• Solido Simulation Suite, including Solido SPICE and Analog FastSPICE (AFS) platform for SPICE-accurate verification of analog, RF and 3D-IC designs, and Solido (LibSPICE) for SPICE-accurate batch verification of Library IP and memory-bitcell designs. Further, Solido SPICE and AFS extend support for the industry-standard Open Model Interface (OMI) across Samsung Foundry’s processes from 14nm to 2nm, for enabling aging modeling and reliability analysis.
• Aprisa for digital implementation featuring proven correlation with Calibre sign-off tools, and support for all the design rules and features of Samsung Foundry’s advanced process technology platforms.
• In addition, Calibre and Solido are qualified for Samsung’s latest, fully depleted-silicon on insulator (FD-SOI) process technologies including 18FDS and above.

"As the landscape of integrated circuit design and manufacturing grows ever more dynamic, collaboration between industry partners becomes vital in fulfilling complex customer needs," said Juan C. Rey, Senior Vice President and General Manager, Calibre product line, Siemens Digital Industries Software. "Our collaboration with Samsung Foundry exemplifies this collaborative spirit, where we are advancing the benefits of 3D-IC architectures and other cutting edge technologies, together. These strides, coupled with a suite of new Siemens EDA product certifications and innovative design strategies, empower our customers to outperform in fiercely competitive global markets."

Siemens EDA and Samsung Foundry: expanded collaborations and innovative joint solutions

Siemens and Samsung Foundry's collaboration also extends to shared study and the creation of several new joint solutions to address some of the most pressing challenges in the semiconductor industry, including:

Unlocking the potential of Silicon Photonics - Siemens and Samsung jointly developed innovative photonic verification techniques through modifications to existing toolsets. Siemens’ Calibre equation-based DRC software can apply complex checks to eliminate false errors in curved segments, which are common in silicon photonics. Recognizing the complexity of foundry rule deck modifications, Siemens devised an innovative approach using Calibre Auto-Waivers software to automatically filter out false violations, reporting only real issues.

Automated layout modification addressing hotspots identified through EM/IR analyses: Siemens and Samsung have developed an advanced automated layout modification solution using Calibre DesignEnhancer software, which integrates comprehensive DRC expertise with intelligent layout adjustments to address hotspots from EM/IR analyses and deliver DRC clean results. The solution offers options like DE Via for minimizing IR drop, DE Pge for optimizing power structures to meet EM/IR targets, and DE Pvr for efficient insertion of DCAP and Filler cells, significantly reducing physical verification time.

Siemens’ Tessent™ design for test (DFT) teams collaborated with Samsung Foundry to enable advanced process test and diagnosis using Siemens Tessent Diagnosis and Hi-Res Chain software. New defects in complex manufacturing require effective screening and defect understanding. Samsung Foundry's predictive approach to screen defects, combining Tessent test and diagnosis, dramatically increases defect prediction while substantially reducing test cost. Tessent cell-aware test was able to increase the defect coverage significantly; and Hi-Res chain diagnosis further improved diagnosis resolution by enabling quick identification of hidden systematic defects. This collaboration for yield learning is focused on fault models for advanced processes used in the  latest semiconductor devices.

Multi-die Innovations for through-silicon via (TSV) and silicon interposer based designs: Recent Siemens and Samsung collaboration focused on aligning Siemens’ Innovator3D™ IC solution, a multi-die planning, simulation and verification integrator platform, with Samsung’s evolving heterogeneous integration methodology. The efforts included developing new checks for verifying inter-chip antenna effects and electrostatic discharge (ESD) with advanced features of the Calibre 3DSTACK solution, and automating Calibre 3DSTACK xACT flow to improve cross multi-die parasitic extraction efficiency, accuracy and consistency particularly for, but not limited to, TSV and interposer based 2.5D/3D design implementation.

The partners collaborated on experiments utilizing the SVDB from LVS runs along with SPICE models to calculate variations in threshold voltage and mobility for each device based on the local layout effects (LLE) parameter values. Using this approach to identify failed devices without running post-layout simulation has proven effective in detecting real issues during design phase, particularly in standard cells and analog designs. It has gained significant traction from Samsung design teams and is already supported for many process nodes from 14nm to 2nm.

New reference flows for mutual customers. Siemens’ Solido Custom IC team and Samsung Foundry collaborated to create multiple new reference flows to enable mutual customers on verification setups and methodologies with advanced process nodes. These include:

Solido Simulation Suite demonstrates analog circuit verification flows with Solido SPICE and AFS using transient and RF analyses, as well as Standard-cell verification flow with Solido LibSPICE software using Monte Carlo transient analysis.

Solido Design Environment demonstrates a SPICE-level variation-aware verification flow including Sample Reduced Monte Carlo, High-Sigma Extraction, Design Sensitivity and Optimization.

Solido Characterization Suite software, which demonstrates .lib production with Solido Generator and .lib verification and analysis using Solido Analytics.

Solido IP Validation Suite demonstrates production sign-off quality IP QA for in-view, cross-view and version-to-version validation.