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Connect the Dots: Sequential Lamination in HDI PCB Manufacturing

As HDI technology becomes mainstream in high-speed and miniaturized electronics, understanding the PCB manufacturing process can help PCB design engineers create successful, cost-effective designs using advanced technologies. Designs that incorporate blind and buried vias, boards with space constraints, sensitive signal integrity requirements, or internal heat dissipation concerns are often candidates for HDI technology and usually require sequential lamination to satisfy the requirements. This complex multilayer construction technique enables finer features, dense interconnects, and multiple layers of microvias and buried vias within a single design. However, it’s also a source of significant cost and potential yield loss if not thoughtfully designed.

Sequential Lamination and the Importance for HDI Designs
In sequential lamination, a stepwise build-up process enables connections on specific layers. Figure 1 shows a simple representation of the via structures where sequential lamination proves effective. This design uses buried vias from layers 2–5, microvias on layers 1 and 6, and through-hole vias from layer 1 to layer 6. 

Figure 1: A design using buried vias from layers 2–5, microvias on layers 1 and 6, and through-hole vias from layer 1 to layer 6.

To build this design, we will need to use a sequential lamination process. The first step is to create the image on copper layers 3 and 4. We will use our standard single-sided inner layer process. Photoresist is applied to both sides of the cores, representing layers 2 and 3, and layers 4 and 5. We then image the copper layers on 3 and 4 using our LDI (laser direct imaging) process. We flood and expose layers 2 and 5 so that all the copper will remain after etching. We then etch the copper circuitry into layers 3 and 4. We laminate these cores together with the appropriate prepreg layers, creating a multilayer sub-assembly (sub).

To create the buried vias, we will drill through-holes on our newly created sub-assembly from layers 2 to 5. We then process the sub through electroless copper deposition, which adds a thin conductive layer of copper inside the drilled holes, enabling electroplating later in the process. The sub then goes through imaging again, but this time, instead of applying a full image, we only expose the through-holes. This allows us to plate copper into the holes without affecting the surface copper on layers 2 and 5. After the copper is plated, we remove the resist, thereby exposing the underlying copper. The sub then goes through epoxy via filling and copper planarization. The panel then returns to imaging to create the copper circuitry on layers 2 and 5. Next, we etch the sub-panel, strip the photoresist, and prepare it for re-lamination. This time, pre-preg is applied to both sides of the sub build, and we add copper foil to the outside surfaces to form layers 1 and 6. We then press the parts, and the panel is ready for microvia creation.

For the microvias, the panel is first sent to imaging, where we apply a photoresist with an image consisting only of dots, each representing the diameter of a microvia. The etching process removes these dots, which removes the copper and exposes the laminate underneath. We remove the resist, and the panels are ready for the laser process.

CNC lasers are used to ablate the dielectric material down to the copper landing pad. Ablating all the dielectric material is important, but it’s also important not to overdo the process. Once the lasing process is complete, we drill through-holes in the panels. Aligning the laser-drilled microvias and these holes to the sub below is critical for making good PCBs.

After creating the holes, thorough cleaning removes laser residue and activates the copper on the panels, preparing them for plating. Then, we re-process them through the electroless copper process. With metal now in the through-holes and microvias, the panels go through another imaging step to create the circuitry on the external layers. Once imaged, we copper electroplate the parts (covering the circuitry, through-holes, and microvias), then electroplate with tin to protect the newly added copper. We remove the photoresist, etch away the copper below, and remove the tin. At this stage, the panels are ready for inspection and solder mask application. This is one process sequence for the most basic sequentially-laminated structures. Some designs or requirements may alter this process sequence. 

Yield Detractors

The added processing steps for the sequential laminated parts impact lead times and cost. Here are some potential areas where yield loss is possible in the manufacturing process.

Via reliability failures

• Registration, especially with stacked microvias
• Insufficiently plated vias or voids in via-fill

Delamination

• Inadequate bonding between layers

Registration issues

• Misalignment between layers due to multiple processes

A general rule of thumb for setting expectations on lead time: Every required lamination process adds a week to the lead time.

Cost Drivers

Unsurprisingly, sequential lamination is one of the most expensive cost drivers in the PCB manufacturing process. Here are cost drivers to consider when designing:

The number of lamination cycles

• Each cycle adds material, tooling, processing time, and QA steps
• Reducing build-up cycles can dramatically lower the cost

Via structure type

• Stacked microvias require more processing (via fill, planarization) and tighter controls, increasing cost
• Staggered microvias are more cost-effective and reliable

Via filling and planarization

Tight tolerances

• High aspect-ratio vias, narrow trace/space (<3 mil), and tight annular rings require advanced fabrication techniques and add yield risk

Material selections

• High-Tg or low-loss materials can drive up material costs and potentially lead times
• Asymmetric stack-ups or non-standard stack-ups add complexity

Tips for Design 
To optimize for manufacturability, yield, and cost:

• Minimize lamination cycles: Use fewer HDI layers if possible. Consider 1+N+1 or 2+N+2 instead of 3+N+3
• Use staggered microvias: Reduce via fill complexity and enhance reliability
• Balance stack-up symmetry: Minimize warpage by mirroring dielectric and copper weights
• Avoid tight drill-to-copper tolerances: Maintain generous spacing around vias, especially buried or stacked
• Validate via aspect ratios: Keep mechanical and laser vias within fab capability, typically 1:1 or less
• Engage early with your fabricator: Co-design the stackup and via structure with the fab shop

Conclusion
Sequential lamination unlocks the design flexibility needed for HDI products but comes with a steep cost and reliability burden if not well-managed. For PCB design engineers, the key is to design with manufacturing in mind. Reduce unnecessary lamination cycles, simplify via structures, and ensure the design team aligns stack-up symmetry and tolerances with fabrication capabilities.

Partnering closely with your PCB fabricator and involving them early in the design phase can mean the difference between a smooth ramp to production and months of yield-chasing rework.

Read Matt’s book, The Printed Circuit Designer’s Guide to… Designing for Reality, or listen to his podcast here.

This column originally appeared in the July 2025 issue of Design007 Magazine.