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Defense Speak Interpreted: If CHIPS Cuts Back, What Happens to Electronics Packaging Funds?

In my May column, I examined the topic of the CHIPS Act and its current status as a U.S. government program. I found that CHIPS activities continue, but some corporations have delayed or canceled them because of budget cuts or corporation-specific problems. However, CHIPS integrated circuits—mostly administered by the Department of Commerce—don’t fully drive the electronics interconnection activity being funded by the government. Let’s cover the progress/status of other programs: 

DPA Title III: The Most Direct Funding Mechanism
The March 27, 2023, Memorandum on Presidential Determination Pursuant to Section 303 of the Defense Production Act of 1950, as amended, on Printed Circuit Boards and Advanced Packaging Production Capability, enabled the Department of Defense (DoD) to grant funds for printed circuit board supply in the United States.

Purpose

DPA Title III allows the DOD to invest in advanced microelectronics capacity, ensuring the production of state-of-the-art integrated circuits within the U.S.
Motivation

The action stems from the need to enhance national defense capabilities, address supply chain vulnerabilities identified in a 2021 executive order on supply chains, and boost the competitiveness of the American electronics industry.

Impact on PCBs

DPA Title III investments aim to strengthen the domestic manufacturing of PCBs, reducing reliance on foreign sources and bolstering the U.S. Defense Industrial Base.

Examples of Investments:

• The DOD gave $39.9 million to Calumet Electronics Corporation to expand production of high-density build-up (HDBU) substrates, for radar and electronic warfare.
• TTM Technologies received $30 million to boost its expansion in Central NY for manufacturing advanced PCBs, creating a secure supply chain for the defense and semiconductor industries 
• GreenSource Fabrication received a $46.2 million DoD grant through the Defense Production Act Investment (DPAI) Program in December 2023 to expand its capacity to manufacture advanced electronic components, specifically HDI PCBs and integrated circuit substrates.
• An $11.7 million award went to Ensign-Bickford Aerospace & Defense (EBAD) to expand its PCB assembly (PCBA) production capacity for hypersonic weapons.

Congressional Support

While facing budgetary challenges, Congress has shown some support for DPA funding for advanced packaging and PCBs in FY24, and efforts are ongoing to secure continued and robust funding.

Challenges

The defense industry is risk-averse, hesitant to embrace new suppliers until they prove to be reliable and cost-effective. Additionally, issues like reliance on lead-based solders and reliability concerns with microvias persist. 

Overall, DPA Title III is addressing critical supply chain vulnerabilities related to printed circuit boards and advanced packaging by investing in and strengthening the domestic manufacturing capabilities of these vital electronic components.

CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Awards
The CHIPS NAPMP has finalized $1.4 billion in award funding to bolster U.S. leadership in advanced packaging and enable new technologies to be validated and transitioned at scale to U.S. manufacturing. These awards will help establish a self-sustaining, high-volume, domestic, advanced packaging industry where advanced node chips are both manufactured and packaged in the United States.

The awards include:

• A total of $300 million under the CHIPS NAPMP’s first Notice of Funding Opportunity (NOFO) for advanced substrates and material research to Absolics Inc., Applied Materials Inc., and Arizona State University.
• $1.1 billion to Natcast to operate the advanced packaging capabilities of the CHIPS for America NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility (PPF). This will be in Arizona. 

The proposed projects are:

Absolics, Inc. in Covington, Georgia: Absolics plans to revolutionize glass core substrate panel manufacturing by developing cutting-edge capabilities in partnership with over 30 partners, including academic institutions, large and small businesses, and non-profit entities, having been recognized as the recipient in the glass materials and substrates areas, with up to $100 million in potential funding. Through its Substrate and Materials Advanced Research and Technology (SMART) Packaging Program, Absolics aims to build a glass-core packaging ecosystem.

In addition to developing the SMART Packaging Program, Absolics and its partners plan to support education and workforce development efforts by bringing training, internship, and certification opportunities into technical colleges, the HBCU CHIPS Network, and Veterans programs. Through these efforts, Absolics would leapfrog the current glass core substrate panel technology and support investments in a future high-volume manufacturing capability.

Applied Materials in Santa Clara, California: Applied Materials, along with a team of 10 collaborators, is working on developing and scaling a disruptive silicon-core substrate technology for next-generation advanced packaging and 3D heterogeneous integration.

Applied’s silicon-core substrate technology has the potential to advance America’s leadership in advanced packaging and help catalyze an ecosystem to develop and build next-generation energy-efficient artificial intelligence (AI) and high-performance computing (HPC) systems in the US. In addition, Applied Materials’ education and workforce development plan is designed to strengthen the training and internship pipeline in the US between state universities and the semiconductor industry.

Arizona State University: ASU is developing the next generation of microelectronics packaging through fan-out-wafer-level-processing (FOWLP). At the ASU Advanced Electronics and Photonics Core Facility, researchers are exploring the commercial viability of 300 mm wafer-level and 600 mm panel-level manufacturing, a technology that does not exist as a commercial capability in the U.S. today.

ASU’s team of over 10 partners, led by industry pioneer Deca Technologies, is in a regional stronghold for microelectronics manufacturing and comprises large and small businesses, universities and technical colleges, and non-profits. This team spans the entire United States with industrial leaders in materials, equipment, chiplet design, electronic design automation, and manufacturing. 

NGMM—DARPA
The Next-Generation Microelectronics Manufacturing program, (NGMM), aims to unlock accessible prototyping for the microelectronics of tomorrow by establishing the first-ever national center for advancing U.S.-based 3D heterogeneous integration (3DHI). I define three-dimensional chip stacking as a form of “interconnection packaging.”

Given the agency’s expectation that future innovation hinges on the fusion of diverse materials, devices, and circuits through advanced packaging, 3DHI will be key to U.S. technological leadership. The foundational goal of NGMM is to establish a self-sustaining manufacturing center for R&D and pilot production of high-performance 3DHI microelectronics.

DARPA is working with the University of Texas at Austin and its existing Texas Institute for Electronics (TIE) research center to establish the TIE NGMM Center (TNC) to support 3DHI microelectronics research, development, and low-volume production.

The center will leverage partnerships spanning organizations across the defense industrial base, domestic foundries, vendors and startups, designers and manufacturers, members of academia, and other stakeholders to achieve a shared vision for national and economic security. The center encompasses both a physical location and a research pipeline to drive dual-use innovations supporting the defense sector, academia, and industry.

In Phase 0 of NGMM, conducted in 2023, performer teams worked to define, analyze, and make expert recommendations for representative 3DHI systems. Their work informed the next phases of creating a domestic center for fabricating 3DHI micro systems.

Phases 1 and 2 are 2.5 years long. Phase 1, awarded on July 11, 2024, will establish the center’s infrastructure and basic capabilities. Phase 2 will focus on building 3DHI prototypes and automating essential processes to drive long-term success. The official kickoff for NGMM Phase 1 took place in September 2024 in Austin.

Re-shore Ecosystem for Secure Heterogeneous Advanced Packaged Electronics (RESHAPE) is a DoD initiative.

1. Goal
   • Revitalize and enhance the domestic advanced packaging manufacturing ecosystem for U.S. semiconductors.
2. Key features
   • Focuses on "back-end-of-line" processes for 300 mm wafer diameter capabilities.
   • Aimed at low-volume/high-mix production of secure 2.5 and/or 3D advanced packaging solutions.
3. Awards and Funding
   • Initial contracts were awarded in January 2024 to Micross Components and the government of Osceola County, Florida, totaling $49 million.
   • Awards made through the Industrial Base Analysis and Sustainment (IBAS) program.

State-of-the-art Heterogeneous Integrated Packaging (SHIP)
A DoD program is partnering with Intel and Qorvo to develop and provide advanced microelectronics for military systems. Intel leads the SHIP Digital effort, creating multi-chip packages (MCPs) with advanced digital chiplets and Intel Agilex FPGAs, while Qorvo leads SHIP-RF, developing advanced RF packaging through heterogeneous integration. The goal is to integrate modern commercial microelectronics into the defense industrial base, ensuring future national security needs are met with faster, smaller, and more efficient components.

Purpose of the SHIP Program

• Commercial leverage: To leverage the commercial industry's advanced packaging capabilities, including Intel's digital and Qorvo's RF expertise, to meet specific DOD requirements. 
• Cost & SWaP savings: To develop prototypes with enhanced capabilities and improved size, weight, and power (SWaP) characteristics beneficial to war fighters. 

Intel's Role (SHIP Digital) 

• MCP-1 and MCP-2: Intel is developing Multi-Chip Packages (MCPs) containing advanced digital chiplets and Intel Agilex FPGAs.
• Capabilities: Focuses on creating a catalog of available chiplets, package types, and designs for reuse and standardization.

Qorvo's Role (SHIP-RF)

• MCM-1: Qorvo is developing Multi-Chip Modules (MCMs) like MCM-1. 
• Advanced packaging: will enhance Qorvo's Advanced Microwave Module Assembly (AMMA) facility with new process capabilities and capacity for heterogeneous RF packaging. 
• Design center: will establish a design center with simulation and layout tools, including design kits, to support customers in developing new designs. 

How It Works

• Strategic partnerships: The DOD, through the S²MARTS Other Transaction Agreement (OTA), partners with Intel, Qorvo, and BAE Systems. 
• STAMP pilot: The System Transition Acceleration Program initiative gives DIB partners early access to the prototypes to accelerate their integration into DOD systems. 

Defense Business Accelerator (DBX) Microelectronics Challenge
The U.S. Partnership for Assured Electronics (USPAE) has awarded grants to electronics companies through initiatives like the Defense Business Accelerator (DBX) Microelectronics Challenge to commercialize dual-use technologies and strengthen the domestic microelectronics supply chain.

Source: Microelectronics Commons

In late 2023, USPAE and the DoD awarded nearly $10 million to seven microelectronics firms to commercialize technologies with both commercial and military applications. The DBX challenge aims to accelerate the growth of domestic microelectronics businesses by focusing on hardware-intensive, early-stage technologies and scaling them with private capital. 

The Microelectronics Commons is celebrating three years, with $740 million invested in 34+ technical projects. This means projects are in the $20 million range, not nearly what a wafer fab costs. Also, over 90 workforce development initiatives are part of Microelectronics Commons. Commons was authorized by CHIPS, but administered by Defense, not Commerce. Each hub has a focus topic, and hub members come from all over the United States.

Commons uses a dual concept: cores with demonstration capability and hubs with research and design ties. With eight hubs, this is about four projects per hub. Together, this sounds like a lot, but in terms of a project, $20 million will buy a fair amount of research, a few pieces of equipment each, but not much brick and mortar. I believe microelectronics hubs remain a “matchmaker” activity where like-minded individuals can tackle an idea together. The Microelectronics Commons Annual Meeting is Oct. 27–29 in Washington, D.C.

Denny Fritz was a 20-year direct employee of MacDermid Inc. and retired after 12 years as a senior engineer supporting the Naval Surface Warfare Center in Crane, Indiana.