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Fresh PCB Concepts: Choosing Via Types—A Practical Guide for PCB Engineers 

When you first learn PCB routing, vias look like plumbing: holes that let signals pass between layers. As designs become denser and products shrink, vias develop from simple interconnects into deliberate engineering choices. Selecting between through-hole, blind, buried, microvia, or advanced options like skip vias is a balancing act between electrical performance, manufacturability, cost, and long-term reliability. In HDI boards, via strategy is as consequential as the stackup, material selection, or component placement. 

Here are the practical trade-offs and process realities that should drive via selection, with an emphasis on how fabrication choices and IPC guidance shape what’s possible.

At their simplest, vias fall into these broad categories:

• Through-vias penetrate the entire board and remain the cheapest and most forgiving option
• Blind vias connect an outer layer to one or more inner layers but stop short of the opposite side
• Buried vias connect only internal layers and are invisible from the outside

Microvias are a miniaturized subset, typically laser-drilled and limited to a single dielectric layer. They enable HDI architectures but come with narrow aspect-ratio, dielectric, and plating requirements.

These definitions are not academic. Fabricators and IPC documents explicitly define allowable geometries and process windows, so designers must be familiar with them before routing begins.

Through-vias are attractive because they’re robust and inexpensive, but they occupy valuable inner-layer real estate and can force thicker stackups when many signals require routing. When a BGA becomes dense, routing outward to the board edge is often unfeasible. Instead, designers use blind, buried, or microvias to create escape routes without consuming every layer. Blind and buried vias free up internal copper for signal traces and planes, and microvias push that capability further, enabling HDI stackups like 1+n+1 or 2+n+2 that pack more routing under BGAs and reduce board size. 

The material manufacturing of vias shapes cost and reliability. Traditional through, blind, and buried vias often use mechanical drilling. Microvias, however, are nearly always laser-drilled (CO₂ or UV) because mechanical drills struggle at tiny diameters and shallow depths. Modern fabs typically combine both methods: mechanical drilling, where robustness is required, and laser drilling for HDI features. Laser processes permit very small diameters and precise depths, but they introduce distinct metallization, cleaning, and process-control demands that must be met to achieve reliable plating.

A major cost and reliability driver in HDI designs is the number of lamination or press cycles. Each additional dielectric buildup often requires another lamination, laser-drilling pass, and plating step. These sequential operations increase material and processing costs, add lead time, and introduce additional registration and warpage risk. Minimizing lamination steps while meeting routing needs is therefore a practical optimization. The fewer press cycles, the lower the cost and the fewer opportunities for misregistration or dimensional drift.

Within HDI architectures, designers must choose between stacked and staggered microvias. Stacked microvias place microvias directly on top of one another to conserve footprint, but they require near-perfect registration and plating precision. Each stacked layer usually demands another lamination cycle, increasing cost and process complexity. Staggered microvias offset the vias between adjacent layers. This approach is more forgiving, distributes mechanical stress better under thermal cycling, and is less risky from a manufacturing viewpoint. Many fabricators recommend staggered designs for improved reliability unless the product’s form factor requires the footprint savings of stacking.

There is also a lesser-known but useful option, the skip via,—a laser-drilled microvia that bypasses an intermediate layer, for example, connecting Layer 1 to Layer 3 in a single drilling step. Skip vias can save process time and reduce the number of sequential build steps, but they push fabrication limits. Because a skip via traverses a greater depth, its aspect ratio (depth to diameter) grows. When that ratio approaches or exceeds about 1:1, uniform copper plating becomes difficult. The risk of thin copper walls or voids rises, which can compromise reliability. Skip vias demand extremely tight laser depth control, uniform dielectric thickness, and proven plating chemistry. Only use skip vias when your fabricator validates both drilling precision and plating yields; otherwise, sequential stacked or staggered microvias are the safer choice.

Microvias are the go-to tool for dense BGAs, ultra-fine-pitch chips, and RF modules where short interconnects and controlled impedance matter. Their small size is reduced via stub inductance and improves signal integrity, but they bring stricter requirements for registration, dielectric thickness, and plating quality, and they are more expensive. Typical fabrication rules limit microvia depth to around 0.25 mm from capture land to target land, and dielectric thicknesses are usually in the tens of microns, though specifics vary by fabricator. Always confirm your fab’s detailed design rules early in the layout phase.

Blind vias occupy a practical middle ground. They enable surface-to-inner-layer connections without passing through the entire board, facilitating BGA breakout without complete HDI complexity. You can drill blind vias mechanically or by laser, depending on diameter and depth, and may require tenting or filling if exposed on the surface. They cost more than standard through-vias but typically less than full microvia HDI processes, making them attractive for mixed-density boards where only portions of the board need high routing density.

Buried vias connect internal layers only and are formed and plated before outer-core lamination, which adds processing steps and inspection. Each buried-via stage typically equates to an extra lamination cycle before outer layers are bonded, increasing both material cost and production time. Buried vias commonly appear in large, complex multilayer systems (backplanes and high-reliability equipment) where internal isolation, controlled impedance, and reliability outweigh the higher fabrication complexity.

Via-in-pad is another important consideration. Placing vias directly within component pads solves many routing challenges, especially under dense BGAs, but unfilled via-in-pad allows solder to wick into the via barrel, creating voids and unreliable joints. The standard remedy is via filling and capping—epoxy or copper fill—plated over to leave a flat, solderable surface. Filled via-in-pad is mature but costlier and thermally demanding. It requires validated filling processes, robust cleaning, and careful thermal profiling during reflow. Use via-in-pad only when necessary and only with a fabricator capable of consistent via filling and capping.

Standards and procurement language matter. IPC-2221A provides basic design rules for pad dimensions and spacing. IPC-4761 classifies via protection and filling options—tented, capped, or filled—and gives a common vocabulary for specifying via treatments. IPC-6012F sets qualification and performance classes (Class 1/2/3) that determine acceptance criteria and drive process discipline. For Class 3 applications, where there is an expectation of mission-critical reliability, fabricators must demonstrate process control across drilling and lamination cycles, because each additional press cycle adds dimensional variation requiring management and verification.

So, how should you choose? If cost is paramount and density is modest, through-vias are the best choice. Many larger BGAs—pitches of about 0.8 mm and above—can escape using only through-hole vias with careful fanout. As BGA pitch shrinks below roughly 0.5 mm, routing channels narrow and HDI techniques become essential. Microvias, and where your fabricator supports them, skip vias, allow breakout without adding bulky layers, though they force tighter process discipline and higher cost. Blind vias are a pragmatic compromise when you need partial HDI. Buried vias and hybrid strategies (selective microvias plus plated buried vias) are better for high-reliability, high-layer-count assemblies.

A practical via strategy is meaningless without early collaboration with your fabricator. Not all shops offer the same laser-drilling, registration, or via-filling capabilities. Stacked microvias, skip vias, and filled via-in-pad may carry significant premiums or be unsupported. Discuss the expected number of lamination cycles, acceptable aspect ratios, via-fill tolerances, and plating specifications during stack-up planning. These conversations avoid late-stage redesigns, prevent yield surprises, and align your electrical goals with real-world process windows.

Ultimately, selecting via types is an engineering negotiation between electrical intent, mechanical constraints, assembly strategy, and manufacturing reality. Think of via choices as choreography. They must coordinate with stack-up decisions, component placement, signal-integrity needs, and supplier capabilities. Communicate the expected service environment and reliability requirements up front, ask producers for capability proofs or process flow summaries, and lock IPC-referenced acceptance criteria into purchase orders. With that approach, via selection becomes a deliberate instrument to meet electrical function and manufacturable reality rather than a source of post-layout regret.

Ramon Roche is a field applications engineer with NCAB Group.