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Advanced Packaging and the New Scaling Walls

09/17/2026 | Chetan Arvind Patil, Marvell Technology
Advanced packaging is becoming the foundation for semiconductor scaling in the AI era. As monolithic processors encounter practical limits around reticle size, yield, memory bandwidth, power, and cost, the industry is moving toward architectures built from multiple compute dies, HBM stacks, I/O chiplets, and heterogeneous packaging solutions. The result is that semiconductor scaling is no longer determined only by how much functionality can be integrated into a single die, but by how much silicon can be integrated efficiently within a package.

GSME Joined TSMC OIP Value Chain Alliance in North America

09/16/2026 | PRNewswire
GS Microelectronics U.S., Inc. (GSME), a leading semiconductor solutions provider, announced it has officially joined TSMC's Open Innovation Platform® (OIP) Value Chain Alliance (VCA) as a member partner in North America.

Spirox Launches High-Speed TGV Crack Inspection System to Support High-Volume Glass Substrate Inspection

09/16/2026 | PRNewswire
Spirox, hosted the Advanced Packaging Technology Forum, bringing together experts from Corning and DNP to share insights on Glass Core, TGV, reliability, and inspection technologies for next-generation AI and HPC applications.

Celebrating One Year of the Advanced Electronic Packaging Technology Council (ADEPT): From Momentum to Measurable Impact

09/15/2026 | Devan Iyer, Global Electronics Association
Nearly 15 months ago, we launched the Advanced Electronic Packaging Technology Council with a simple premise: the packaging challenges facing our industry are moving too fast—and spanning too many disciplines—for any single company, region, or segment to solve alone. What we’ve seen since then is proof that focused, industry-led collaboration can turn urgency into alignment, and alignment into action.

Closing the Gap: Measuring 20-µm Spacing in Advanced SiP Packaging

09/18/2026 | Axel Lindloff, Koh Young Europe
Twenty microns does not leave much room for error. As advanced packaging increases functional density, the distance between neighboring devices is shrinking to dimensions that create an entirely new set of inspection challenges. In some system-in-package (SiP) applications, components approximately 200 to 300 µm tall can be separated by gaps of only 20 to 30 µm. Measuring those spaces accurately requires considerably more than simply increasing camera magnification. The challenge is optical access.
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