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Advanced Chip and Circuit Materials (ACCM) introduced Celeritas SMC (Silicon-Matched Core), a production-ready core for advanced IC substrates engineered to match the in-plane coefficient of thermal expansion of silicon while running on established organic-substrate manufacturing lines. Available now from ACCM's Wisconsin facility, the material is designed for large-body chiplet packages, embedded-bridge architectures, and other advanced packages in which conventional organic cores face growing warpage and thermomechanical reliability limits.
Celeritas SMC provides the low CTE, stiffness, dimensional stability, and electrical performance that have driven industry interest in glass core, without requiring through-glass vias, glass-specific metallization, brittle-panel handling, or wholesale line retooling.
Why advanced packaging needs a new core
AI and high-performance computing packages are growing faster than the materials beneath them. As package bodies exceed 100 mm per side and silicon bridge dies are embedded directly into the substrate, the thermal expansion mismatch between a conventional organic core at 12 to 16 ppm/°C and silicon at roughly 3 ppm/°C drives warpage, embedding stress, and interconnect fatigue that packaging engineers can no longer design around. The industry consensus is clear: the core must move toward the CTE of silicon.
Glass core emerged as one route to that goal, and its target properties are real. Its commercialization, however, depends on glass-specific via formation, metallization, inspection, surface-preparation, and handling capabilities that are not broadly deployed in high-volume substrate manufacturing, together with substantial new capital investment across the supply chain. Celeritas SMC delivers the silicon-matched CTE, dimensional stability, and electrical performance sought from glass core through the manufacturing infrastructure the industry already operates.
Silicon-matched performance without process reinvention
Celeritas SMC matches silicon from room temperature to 100 °C and is tunable by construction, eliminating the bulk in-plane CTE mismatch between embedded silicon and the core. Vias are formed by standard mechanical and laser drilling. Build-up films bond directly using established lamination processes, without glass-specific surface preparation or adhesion-promotion steps. Panels handle, laminate, and singulate on the installed equipment base using the process fabricators already use.
The property set extends well beyond CTE: a glass transition temperature above 300 °C for compatibility with the full assembly and rework thermal budget, a high stiffness, a dissipation factor of 0.004 at 10 GHz with lower loss grades available for the most demanding signal integrity applications, moisture absorption of 0.1 percent at saturation, and core thicknesses from 100 to 1,200 µm and above, covering everything from thin coreless-adjacent constructions to thick high-rigidity platforms for the largest package bodies.
Performance without the glass-core capital burden
“The industry does not have a low CTE problem, it has a low CTE at acceptable cost problem,” said Tarun Amla, PhD, Founder, President, and CEO of ACCM. “Glass core asks the entire substrate supply chain to retool around through-glass vias before volume yields and economics have been established. Celeritas SMC gives packaging engineers silicon-matched CTE, high stiffness, and low loss on the equipment they already own, with the drilling, metallization, and lamination processes they already know. That is the difference between a roadmap concept and a material customers can put on their lines today.”
Managing stress across the complete package
A low CTE package does not remove thermomechanical stress from the system; it relocates it. A package pulled down toward silicon CTE transfers the mismatch to the board-level interconnect, which becomes the new reliability bottleneck as package bodies grow and package-to-board integration tightens. ACCM is positioned on both sides of that interface: the same material platform behind Celeritas SMC enables printed circuit boards with tunable CTE from 2 to 10 ppm/°C, allowing a graded CTE architecture from the die through the substrate to the system board. For embedded-bridge designs, CoWoS-L-class constructions, and other large-body chiplet packages, Celeritas SMC enables CTE management within the package substrate. For substrate-free architectures such as CoWoP, the broader ACCM material platform can provide tunable-CTE system-board materials, addressing the package-to-board interface where thermomechanical stress is otherwise concentrated.
Made in America and available now
“Every panel of Celeritas SMC is manufactured in Wisconsin, on a site that has made advanced laminates for American electronics for decades,” said Keshav Amla, Founder and COO of ACCM. “Customers bring us a stackup, we supply material and applications-engineering support, and their fabricator processes it on equipment already installed in the line. Domestic production, direct applications engineering support, and an initial process-verification path measured in weeks give our customers both speed and supply-chain resilience as they plan their next-generation packages.”
Celeritas SMC is available for customer evaluation immediately, in core thicknesses from 100 to 1,200 µm and above. ACCM also offers ultra-low-loss build-up films engineered to pair with the core for customers seeking a complete low-loss, CTE-managed dielectric stack. A technical datasheet and application notes for embedded die and large-body substrate constructions are available under NDA.
